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authorWill Deacon <will.deacon@arm.com>2013-09-04 11:34:08 +0100
committerWill Deacon <will.deacon@arm.com>2014-10-20 18:49:18 +0100
commit1191ccb34cf810a0fefaaf5ca3cfe3c5d7675927 (patch)
tree1700dadabaaa2d658fa0c34580edd6c99e0bb205 /arch/sparc/include/asm/io_64.h
parent5da590574cbc39e48d1b71d87b62766c044b9b52 (diff)
sparc: io: implement dummy relaxed accessor macros for writes
write{b,w,l,q}_relaxed are implemented by some architectures in order to permit memory-mapped I/O accesses with weaker barrier semantics than the non-relaxed variants. This patch adds dummy macros for the write accessors to sparc, in the same vein as the dummy definitions for the relaxed read accessors. The existing relaxed read{b,w,l} accessors are moved into asm/io.h, since they are identical between 32-bit and 64-bit machines. Acked-by: "David S. Miller" <davem@davemloft.net> Acked-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/sparc/include/asm/io_64.h')
-rw-r--r--arch/sparc/include/asm/io_64.h8
1 files changed, 2 insertions, 6 deletions
diff --git a/arch/sparc/include/asm/io_64.h b/arch/sparc/include/asm/io_64.h
index 80b54b326d49..d50e6127325d 100644
--- a/arch/sparc/include/asm/io_64.h
+++ b/arch/sparc/include/asm/io_64.h
@@ -136,6 +136,7 @@ static inline u32 readl(const volatile void __iomem *addr)
}
#define readq readq
+#define readq_relaxed readq
static inline u64 readq(const volatile void __iomem *addr)
{ u64 ret;
@@ -175,6 +176,7 @@ static inline void writel(u32 l, volatile void __iomem *addr)
}
#define writeq writeq
+#define writeq_relaxed writeq
static inline void writeq(u64 q, volatile void __iomem *addr)
{
__asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */"
@@ -183,7 +185,6 @@ static inline void writeq(u64 q, volatile void __iomem *addr)
: "memory");
}
-
#define inb inb
static inline u8 inb(unsigned long addr)
{
@@ -264,11 +265,6 @@ static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned l
outsl((unsigned long __force)port, buf, count);
}
-#define readb_relaxed(__addr) readb(__addr)
-#define readw_relaxed(__addr) readw(__addr)
-#define readl_relaxed(__addr) readl(__addr)
-#define readq_relaxed(__addr) readq(__addr)
-
/* Valid I/O Space regions are anywhere, because each PCI bus supported
* can live in an arbitrary area of the physical address range.
*/