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authorChris Metcalf <cmetcalf@tilera.com>2013-08-02 16:18:58 -0400
committerChris Metcalf <cmetcalf@tilera.com>2013-08-05 16:12:51 -0400
commit523c178edf45fe04d61aa99ac496bc7494b99810 (patch)
tree88a5daec7b9b0da6ec0481e52732a3b8aa862a23 /arch/tile
parent9bbb08faa91db7711614c9cb0983644086b97aca (diff)
tile PCI RC: tilepro conflict with PCI and RAM addresses
Fix a bug in the tilepro PCI resource allocation code that could make the bootmem allocator unhappy if 4GB is installed on mshim 0. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Diffstat (limited to 'arch/tile')
-rw-r--r--arch/tile/kernel/setup.c9
1 files changed, 5 insertions, 4 deletions
diff --git a/arch/tile/kernel/setup.c b/arch/tile/kernel/setup.c
index 68b542677f6a..676e155a0d63 100644
--- a/arch/tile/kernel/setup.c
+++ b/arch/tile/kernel/setup.c
@@ -614,11 +614,12 @@ static void __init setup_bootmem_allocator_node(int i)
/*
* Throw away any memory aliased by the PCI region.
*/
- if (pci_reserve_start_pfn < end && pci_reserve_end_pfn > start)
- reserve_bootmem(PFN_PHYS(pci_reserve_start_pfn),
- PFN_PHYS(pci_reserve_end_pfn -
- pci_reserve_start_pfn),
+ if (pci_reserve_start_pfn < end && pci_reserve_end_pfn > start) {
+ start = max(pci_reserve_start_pfn, start);
+ end = min(pci_reserve_end_pfn, end);
+ reserve_bootmem(PFN_PHYS(start), PFN_PHYS(end - start),
BOOTMEM_EXCLUSIVE);
+ }
#endif
}