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authorKan Liang <kan.liang@linux.intel.com>2020-09-25 06:49:03 -0700
committerPeter Zijlstra <peterz@infradead.org>2020-09-29 09:57:00 +0200
commit8abbcfefb5f7afabab4578bedd7cd400800cb039 (patch)
tree98ae4ff2b707f3f2a187d0bb061f8b8043492d52 /arch/x86/events/intel/uncore.h
parenta3b1e8451d3fd54fe0df661c2c4f983932b3c0bc (diff)
perf/x86/intel/uncore: Split the Ice Lake and Tiger Lake MSR uncore support
Previously, the MSR uncore for the Ice Lake and Tiger Lake are identical. The code path is shared. However, with recent update, the global MSR_UNC_PERF_GLOBAL_CTRL register and ARB uncore unit are changed for the Ice Lake. Split the Ice Lake and Tiger Lake MSR uncore support. The changes only impact the MSR ops() and the ARB uncore unit. Other codes can still be shared between the Ice Lake and the Tiger Lake. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Link: https://lkml.kernel.org/r/20200925134905.8839-1-kan.liang@linux.intel.com
Diffstat (limited to 'arch/x86/events/intel/uncore.h')
-rw-r--r--arch/x86/events/intel/uncore.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/events/intel/uncore.h b/arch/x86/events/intel/uncore.h
index df544bc377ee..83d2a7d490e0 100644
--- a/arch/x86/events/intel/uncore.h
+++ b/arch/x86/events/intel/uncore.h
@@ -568,6 +568,7 @@ void snb_uncore_cpu_init(void);
void nhm_uncore_cpu_init(void);
void skl_uncore_cpu_init(void);
void icl_uncore_cpu_init(void);
+void tgl_uncore_cpu_init(void);
void tgl_uncore_mmio_init(void);
void tgl_l_uncore_mmio_init(void);
int snb_pci2phy_map_init(int devid);