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authorKan Liang <kan.liang@linux.intel.com>2021-06-30 14:08:34 -0700
committerPeter Zijlstra <peterz@infradead.org>2021-07-02 15:58:40 +0200
commit2a8e51eae7c83c29795622cfc794cf83436cc05d (patch)
tree6fdae998a0a01441a70afd443c2abc60cd6c7266 /arch/x86/events/intel/uncore_snbep.c
parentda5a9156cd2a3be2b00f8defb529ee3e35e5769b (diff)
perf/x86/intel/uncore: Add Sapphire Rapids server M3UPI support
M3 Intel UPI is the interface between the mesh and the Intel UPI link layer. It is responsible for translating between the mesh protocol packets and the flits that are used for transmitting data across the Intel UPI interface. The layout of the control registers for a M3UPI uncore unit is similar to a UPI uncore unit. Signed-off-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Andi Kleen <ak@linux.intel.com> Link: https://lore.kernel.org/r/1625087320-194204-11-git-send-email-kan.liang@linux.intel.com
Diffstat (limited to 'arch/x86/events/intel/uncore_snbep.c')
-rw-r--r--arch/x86/events/intel/uncore_snbep.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index 20045ba723b5..14b9b2367725 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -5703,6 +5703,11 @@ static struct intel_uncore_type spr_uncore_upi = {
.name = "upi",
};
+static struct intel_uncore_type spr_uncore_m3upi = {
+ SPR_UNCORE_PCI_COMMON_FORMAT(),
+ .name = "m3upi",
+};
+
#define UNCORE_SPR_NUM_UNCORE_TYPES 12
static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
@@ -5715,7 +5720,7 @@ static struct intel_uncore_type *spr_uncores[UNCORE_SPR_NUM_UNCORE_TYPES] = {
&spr_uncore_imc,
&spr_uncore_m2m,
&spr_uncore_upi,
- NULL,
+ &spr_uncore_m3upi,
NULL,
NULL,
};