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authorThomas Gleixner <tglx@linutronix.de>2020-04-21 21:22:36 +0200
committerThomas Gleixner <tglx@linutronix.de>2020-06-11 15:15:02 +0200
commit865d3a9afe7eddf320e7f61a442864d6efe27505 (patch)
treec9800c78f472be091addac5a29195734a22dd8d5 /arch/x86/kernel/cpu/mce/p5.c
parent75347bb2535a6d5549cc3e436467b7c40d7bb874 (diff)
x86/mce: Address objtools noinstr complaints
Mark the relevant functions noinstr, use the plain non-instrumented MSR accessors. The only odd part is the instrumentation_begin()/end() pair around the indirect machine_check_vector() call as objtool can't figure that out. The possible invoked functions are annotated correctly. Also use notrace variant of nmi_enter/exit(). If MCEs happen then hardware latency tracing is the least of the worries. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexandre Chartre <alexandre.chartre@oracle.com> Acked-by: Peter Zijlstra <peterz@infradead.org> Acked-by: Andy Lutomirski <luto@kernel.org> Link: https://lkml.kernel.org/r/20200505135315.476734898@linutronix.de
Diffstat (limited to 'arch/x86/kernel/cpu/mce/p5.c')
-rw-r--r--arch/x86/kernel/cpu/mce/p5.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/mce/p5.c b/arch/x86/kernel/cpu/mce/p5.c
index eaebc4ce7398..19e90cae8e97 100644
--- a/arch/x86/kernel/cpu/mce/p5.c
+++ b/arch/x86/kernel/cpu/mce/p5.c
@@ -21,10 +21,11 @@
int mce_p5_enabled __read_mostly;
/* Machine check handler for Pentium class Intel CPUs: */
-static void pentium_machine_check(struct pt_regs *regs)
+static noinstr void pentium_machine_check(struct pt_regs *regs)
{
u32 loaddr, hi, lotype;
+ instrumentation_begin();
rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi);
rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi);
@@ -37,6 +38,7 @@ static void pentium_machine_check(struct pt_regs *regs)
}
add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
+ instrumentation_end();
}
/* Set up machine check reporting for processors with Intel style MCE: */