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authorThomas Gleixner <tglx@linutronix.de>2019-04-14 17:59:55 +0200
committerBorislav Petkov <bp@suse.de>2019-04-17 15:01:09 +0200
commit3207426925d2b4da390be8068df1d1c2b36e5918 (patch)
treed595193cc744409685e00ac141d0b67906ffffe3 /arch/x86/kernel/cpu
parent4d68c3d0ecd5fcba8876e8a58ac41ffb360de43e (diff)
x86/exceptions: Disconnect IST index and stack order
The entry order of the TSS.IST array and the order of the stack storage/mapping are not required to be the same. With the upcoming split of the debug stack this is going to fall apart as the number of TSS.IST array entries stays the same while the actual stacks are increasing. Make them separate so that code like dumpstack can just utilize the mapping order. The IST index is solely required for the actual TSS.IST array initialization. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Andy Lutomirski <luto@kernel.org> Cc: Baoquan He <bhe@redhat.com> Cc: "Chang S. Bae" <chang.seok.bae@intel.com> Cc: Dominik Brodowski <linux@dominikbrodowski.net> Cc: Dou Liyang <douly.fnst@cn.fujitsu.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jann Horn <jannh@google.com> Cc: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Kees Cook <keescook@chromium.org> Cc: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: Nicolai Stange <nstange@suse.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Qian Cai <cai@lca.pw> Cc: Sean Christopherson <sean.j.christopherson@intel.com> Cc: x86-ml <x86@kernel.org> Link: https://lkml.kernel.org/r/20190414160145.241588113@linutronix.de
Diffstat (limited to 'arch/x86/kernel/cpu')
-rw-r--r--arch/x86/kernel/cpu/common.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 8243f198fb7f..143aceaf9a9a 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1731,11 +1731,11 @@ void cpu_init(void)
* set up and load the per-CPU TSS
*/
if (!t->x86_tss.ist[0]) {
- t->x86_tss.ist[ESTACK_DF] = __this_cpu_ist_top_va(DF);
- t->x86_tss.ist[ESTACK_NMI] = __this_cpu_ist_top_va(NMI);
- t->x86_tss.ist[ESTACK_DB] = __this_cpu_ist_top_va(DB);
- t->x86_tss.ist[ESTACK_MCE] = __this_cpu_ist_top_va(MCE);
- per_cpu(debug_stack_addr, cpu) = t->x86_tss.ist[ESTACK_DB];
+ t->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF);
+ t->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI);
+ t->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB);
+ t->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE);
+ per_cpu(debug_stack_addr, cpu) = t->x86_tss.ist[IST_INDEX_DB];
}
t->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET;