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authorDave Airlie <airlied@redhat.com>2010-08-02 10:24:46 +1000
committerDave Airlie <airlied@redhat.com>2010-08-02 10:24:46 +1000
commit7827627107aeb629f1a056cb56b17bd4fb789e03 (patch)
treecbd83582abb9120c7ef724bf439916c8bf864e37 /arch/x86/kernel/pci-calgary_64.c
parente190bfe56841551b1ad5abb42ebd0c4798cc8c01 (diff)
parent219de62a1627247fca10789f28902f66cb0b408f (diff)
Merge branch 'drm-radeon-next' of ../drm-radeon-next into drm-core-next
* 'drm-radeon-next' of ../drm-radeon-next: (333 commits) drm/radeon/kms: trivial code style fixes for audio drm/radeon: remove viewport transform from r6xx/r7xx blit emit drm/radeon: group r6xx/r7xx newly sequential blit state drm/radeon: reorder r6xx/r7xx blit state emit to make more regs sequential drm/radeon: r6xx/r7xx move vport clipping to a single packet drm/radeon: group r6xx/r7xx sequential blit state drm/radeon: remove duplicate state emit in r6xx/r7xx blit drm/radeon: add comments to r6xx/r7xx blit state drm/radeon/kms/r7xx: add workaround for hw issue with HDP flush drm/radeon/kms: remove rs4xx gart limit drm: radeon: fix sign bug drm/radeon/kms: check/restore sanity before doing anything else with GPU. drm/radeon: fall back to GTT if bo creation/validation in VRAM fails. drm/radeon/kms: add ioport register access drm/radeon/kms: enable HDMI audio on RS600/RS690/RS740 drm/radeon/kms: track audio engine state, do not use not setup timer drm/radeon/kms/r6xx+: add query for tile config (v2) drm/radeon/kms: fix CS alignment checking for tiling (v2) drm/radeon/kms: add tiling support to the cs checker for r6xx/r7xx drm/radeon/kms: Add crtc tiling setup support for evergreen ...
Diffstat (limited to 'arch/x86/kernel/pci-calgary_64.c')
-rw-r--r--arch/x86/kernel/pci-calgary_64.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c
index 0b96b5589f08..078d4ec1a9d9 100644
--- a/arch/x86/kernel/pci-calgary_64.c
+++ b/arch/x86/kernel/pci-calgary_64.c
@@ -110,7 +110,7 @@ int use_calgary __read_mostly = 0;
* x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256
* x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128
*/
-#define MAX_PHB_BUS_NUM 384
+#define MAX_PHB_BUS_NUM 256
#define PHBS_PER_CALGARY 4
@@ -1056,8 +1056,6 @@ static int __init calgary_init_one(struct pci_dev *dev)
struct iommu_table *tbl;
int ret;
- BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM);
-
bbar = busno_to_bbar(dev->bus->number);
ret = calgary_setup_tar(dev, bbar);
if (ret)