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authorShai Fultheim <shai@scalemp.com>2012-04-20 01:09:11 +0300
committerIngo Molnar <mingo@kernel.org>2012-05-07 15:27:37 +0200
commitddc5681ed33a279fdc188e98e71f0c539f08c6e6 (patch)
treee8c70c59ed3c4c0a466e39e0a3cc26e7fe991351 /arch/x86/kernel/pci-calgary_64.c
parentfebb72a6e4cc6c8cffcc1ea649a3fb364f1ea432 (diff)
x86/cache_info: Fix setup of l2/l3 ids
On some architectures (such as vSMP), it is possible to have CPUs with a different number of cores sharing the same cache. The current implementation implicitly assumes that all CPUs will have the same number of cores sharing caches, and as a result, different CPUs can end up with the same l2/l3 ids. Fix this by masking out the shared cache bits, instead of shifting the APICID. By doing so, it is guaranteed that the generated cache ids are always unique. Signed-off-by: Shai Fultheim <shai@scalemp.com> [ rebased, simplified, and reworded the commit message] Signed-off-by: Ido Yariv <ido@wizery.com> Cc: Borislav Petkov <borislav.petkov@amd.com> Cc: Andreas Herrmann <andreas.herrmann3@amd.com> Cc: Mike Travis <travis@sgi.com> Cc: Dave Jones <davej@redhat.com> Link: http://lkml.kernel.org/r/1334873351-31142-1-git-send-email-ido@wizery.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/kernel/pci-calgary_64.c')
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