diff options
| author | Sean Christopherson <sean.j.christopherson@intel.com> | 2020-02-07 09:37:41 -0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2020-02-12 20:09:43 +0100 |
| commit | 148d735eb55d32848c3379e460ce365f2c1cbe4b (patch) | |
| tree | d03f8d4cba84e19ae4ecd0f92c6056f2a8ae86fa /arch/x86/kvm/mmu/paging_tmpl.h | |
| parent | ffdbd50dca67b1f12d6f531a0eaf2028d793e54f (diff) | |
KVM: nVMX: Use correct root level for nested EPT shadow page tables
Hardcode the EPT page-walk level for L2 to be 4 levels, as KVM's MMU
currently also hardcodes the page walk level for nested EPT to be 4
levels. The L2 guest is all but guaranteed to soft hang on its first
instruction when L1 is using EPT, as KVM will construct 4-level page
tables and then tell hardware to use 5-level page tables.
Fixes: 855feb673640 ("KVM: MMU: Add 5 level EPT & Shadow page table support.")
Cc: stable@vger.kernel.org
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'arch/x86/kvm/mmu/paging_tmpl.h')
0 files changed, 0 insertions, 0 deletions