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authorDaniel Vetter <daniel.vetter@ffwll.ch>2019-10-23 12:02:47 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2019-10-23 12:10:05 +0200
commit2e79e22e092acd55da0b2db066e4826d7d152c41 (patch)
treee7ec9782c0b7831c511af711424126a2b9a4eb07 /arch/x86/lib/delay.c
parentf1b4a9217efd61d0b84c6dc404596c8519ff6f59 (diff)
parent7d194c2100ad2a6dded545887d02754948ca5241 (diff)
Merge v5.4-rc4 into drm-next
Thierry needs fd70c7755bf0 ("drm/bridge: tc358767: fix max_tu_symbol value") to be able to merge his dp_link patch series. Some adjacent changes conflicts, plus some clashes in i915 due to cherry-picking and git trying to be helpful and leaving both versions in. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'arch/x86/lib/delay.c')
-rw-r--r--arch/x86/lib/delay.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/x86/lib/delay.c b/arch/x86/lib/delay.c
index b7375dc6898f..c126571e5e2e 100644
--- a/arch/x86/lib/delay.c
+++ b/arch/x86/lib/delay.c
@@ -113,8 +113,8 @@ static void delay_mwaitx(unsigned long __loops)
__monitorx(raw_cpu_ptr(&cpu_tss_rw), 0, 0);
/*
- * AMD, like Intel, supports the EAX hint and EAX=0xf
- * means, do not enter any deep C-state and we use it
+ * AMD, like Intel's MWAIT version, supports the EAX hint and
+ * EAX=0xf0 means, do not enter any deep C-state and we use it
* here in delay() to minimize wakeup latency.
*/
__mwaitx(MWAITX_DISABLE_CSTATES, delay, MWAITX_ECX_TIMER_ENABLE);