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| author | Joerg Roedel <joerg.roedel@amd.com> | 2009-06-09 10:50:57 +0200 |
|---|---|---|
| committer | Joerg Roedel <joerg.roedel@amd.com> | 2009-06-09 10:50:57 +0200 |
| commit | d2dd01de9924ae24afeba5aa5bc2e08287701df6 (patch) | |
| tree | 3021bf496579a48984666355b59df5e44b42dd32 /arch/x86/mm/pageattr.c | |
| parent | 367d04c4ec02dad34d80452e32e3370db7fb6fee (diff) | |
| parent | 62a6f465f6572e1f28765c583c12753bb3e23715 (diff) | |
Merge commit 'tip/core/iommu' into amd-iommu/fixes
Diffstat (limited to 'arch/x86/mm/pageattr.c')
| -rw-r--r-- | arch/x86/mm/pageattr.c | 13 |
1 files changed, 4 insertions, 9 deletions
diff --git a/arch/x86/mm/pageattr.c b/arch/x86/mm/pageattr.c index 797f9f107cb6..e17efed088c5 100644 --- a/arch/x86/mm/pageattr.c +++ b/arch/x86/mm/pageattr.c @@ -153,7 +153,7 @@ static void __cpa_flush_all(void *arg) */ __flush_tlb_all(); - if (cache && boot_cpu_data.x86_model >= 4) + if (cache && boot_cpu_data.x86 >= 4) wbinvd(); } @@ -208,20 +208,15 @@ static void cpa_flush_array(unsigned long *start, int numpages, int cache, int in_flags, struct page **pages) { unsigned int i, level; + unsigned long do_wbinvd = cache && numpages >= 1024; /* 4M threshold */ BUG_ON(irqs_disabled()); - on_each_cpu(__cpa_flush_range, NULL, 1); + on_each_cpu(__cpa_flush_all, (void *) do_wbinvd, 1); - if (!cache) + if (!cache || do_wbinvd) return; - /* 4M threshold */ - if (numpages >= 1024) { - if (boot_cpu_data.x86_model >= 4) - wbinvd(); - return; - } /* * We only need to flush on one CPU, * clflush is a MESI-coherent instruction that |