diff options
| author | Max Filippov <jcmvbkbc@gmail.com> | 2015-08-24 19:44:46 +0300 |
|---|---|---|
| committer | Chris Zankel <chris@zankel.net> | 2016-03-11 08:53:31 +0000 |
| commit | abfbd89595e91d5108f807e10bbd2152bc55f36b (patch) | |
| tree | fea9190c224b121a092723b450f3d03a9b84a992 /arch/xtensa/boot | |
| parent | 4611bf7eb52599cb7549eed10f1ab609cbcdfa4b (diff) | |
xtensa: xtfpga: fix serial port register width and endianness
Serial port is attached to XTFPGA boards as native endian device, mark
it as such in DTS and pass correct endianness in platform data.
Set register width in DTS to 4, this way it matches the platform data
and works correctly on big-endian CPUs.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'arch/xtensa/boot')
| -rw-r--r-- | arch/xtensa/boot/dts/xtfpga.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/xtensa/boot/dts/xtfpga.dtsi b/arch/xtensa/boot/dts/xtfpga.dtsi index cd0b9e34adc8..be3fd769677a 100644 --- a/arch/xtensa/boot/dts/xtfpga.dtsi +++ b/arch/xtensa/boot/dts/xtfpga.dtsi @@ -60,6 +60,8 @@ no-loopback-test; reg = <0x0d050020 0x20>; reg-shift = <2>; + reg-io-width = <4>; + native-endian; interrupts = <0 1>; /* external irq 0 */ clocks = <&osc>; }; |