diff options
| author | Marc Gauthier <marc@tensilica.com> | 2013-01-05 04:57:17 +0400 |
|---|---|---|
| committer | Chris Zankel <chris@zankel.net> | 2013-02-23 19:12:52 -0800 |
| commit | 2d1c645cc50b8f5a718b24bad9eb3931e7105d12 (patch) | |
| tree | c385e5064cee10f79b9c359ddd99bd5d1b9f838a /arch/xtensa/include/asm/atomic.h | |
| parent | d0b73b488c55df905ea8faaad079f8535629ed26 (diff) | |
xtensa: dispatch medium-priority interrupts
Add support for dispatching medium-priority interrupts, that is,
interrupts of priority levels 2 to EXCM_LEVEL. IRQ handling may be
preempted by higher priority IRQ.
Signed-off-by: Marc Gauthier <marc@tensilica.com>
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
Diffstat (limited to 'arch/xtensa/include/asm/atomic.h')
| -rw-r--r-- | arch/xtensa/include/asm/atomic.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/xtensa/include/asm/atomic.h b/arch/xtensa/include/asm/atomic.h index c3f289174c10..e7fb447bce8e 100644 --- a/arch/xtensa/include/asm/atomic.h +++ b/arch/xtensa/include/asm/atomic.h @@ -7,7 +7,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (C) 2001 - 2005 Tensilica Inc. + * Copyright (C) 2001 - 2008 Tensilica Inc. */ #ifndef _XTENSA_ATOMIC_H @@ -24,11 +24,11 @@ /* * This Xtensa implementation assumes that the right mechanism - * for exclusion is for locking interrupts to level 1. + * for exclusion is for locking interrupts to level EXCM_LEVEL. * * Locking interrupts looks like this: * - * rsil a15, 1 + * rsil a15, LOCKLEVEL * <code> * wsr a15, PS * rsync |