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| author | Max Filippov <jcmvbkbc@gmail.com> | 2022-03-20 09:40:14 -0700 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2022-03-20 09:53:01 -0700 |
| commit | a3d0245c58f962ee99d4440ea0eaf45fb7f5a5cc (patch) | |
| tree | d54d47f0b54b445920c3c3de6e0b66eeafeff666 /arch/xtensa/mm/tlb.c | |
| parent | 7dc0eb0b6d9f3e2b6a560a04f86ef065a4531a9f (diff) | |
xtensa: fix xtensa_wsr always writing 0
The commit cad6fade6e78 ("xtensa: clean up WSR*/RSR*/get_sr/set_sr")
replaced 'WSR' macro in the function xtensa_wsr with 'xtensa_set_sr',
but variable 'v' in the xtensa_set_sr body shadowed the argument 'v'
passed to it, resulting in wrong value written to debug registers.
Fix that by removing intermediate variable from the xtensa_set_sr
macro body.
Cc: stable@vger.kernel.org
Fixes: cad6fade6e78 ("xtensa: clean up WSR*/RSR*/get_sr/set_sr")
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'arch/xtensa/mm/tlb.c')
0 files changed, 0 insertions, 0 deletions