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authorLinus Torvalds <torvalds@linux-foundation.org>2019-07-16 12:17:07 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2019-07-16 12:17:07 -0700
commit3e859477a1db52a0435d06a55fdb54f62d69c292 (patch)
tree057daeae3cc56a459ef5534b8c6cce8181c0c662 /arch/xtensa/mm
parent1ec4013bab89058dcc594dfe7b5a20f5d46bbc5f (diff)
parent775f1f7eacede583ec25ed56e58c4483f2b29265 (diff)
Merge tag 'xtensa-20190715' of git://github.com/jcmvbkbc/linux-xtensa
Pull Xtensa updates from Max Filippov: - clean up PCI support code - add defconfig and DTS for the 'virt' board - abstract 'entry' and 'retw' uses in xtensa assembly in preparation for XEA3/NX pipeline support - random small cleanups * tag 'xtensa-20190715' of git://github.com/jcmvbkbc/linux-xtensa: xtensa: virt: add defconfig and DTS xtensa: abstract 'entry' and 'retw' in assembly code xtensa: One function call less in bootmem_init() xtensa: remove arch/xtensa/include/asm/types.h xtensa: use generic pcibios_set_master and pcibios_enable_device xtensa: drop dead PCI support code xtensa/PCI: Remove unused variable
Diffstat (limited to 'arch/xtensa/mm')
-rw-r--r--arch/xtensa/mm/init.c5
-rw-r--r--arch/xtensa/mm/misc.S78
2 files changed, 40 insertions, 43 deletions
diff --git a/arch/xtensa/mm/init.c b/arch/xtensa/mm/init.c
index b51746f2b80b..79467c749416 100644
--- a/arch/xtensa/mm/init.c
+++ b/arch/xtensa/mm/init.c
@@ -45,10 +45,7 @@ void __init bootmem_init(void)
* If PHYS_OFFSET is zero reserve page at address 0:
* successfull allocations should never return NULL.
*/
- if (PHYS_OFFSET)
- memblock_reserve(0, PHYS_OFFSET);
- else
- memblock_reserve(0, 1);
+ memblock_reserve(0, PHYS_OFFSET ? PHYS_OFFSET : 1);
early_init_fdt_scan_reserved_mem();
diff --git a/arch/xtensa/mm/misc.S b/arch/xtensa/mm/misc.S
index 11a01c3e9cea..6aa036c427c3 100644
--- a/arch/xtensa/mm/misc.S
+++ b/arch/xtensa/mm/misc.S
@@ -30,7 +30,7 @@
ENTRY(clear_page)
- entry a1, 16
+ abi_entry_default
movi a3, 0
__loopi a2, a7, PAGE_SIZE, 32
@@ -44,7 +44,7 @@ ENTRY(clear_page)
s32i a3, a2, 28
__endla a2, a7, 32
- retw
+ abi_ret_default
ENDPROC(clear_page)
@@ -57,7 +57,7 @@ ENDPROC(clear_page)
ENTRY(copy_page)
- entry a1, 16
+ abi_entry_default
__loopi a2, a4, PAGE_SIZE, 32
@@ -86,7 +86,7 @@ ENTRY(copy_page)
__endl a2, a4
- retw
+ abi_ret_default
ENDPROC(copy_page)
@@ -116,7 +116,7 @@ ENTRY(__tlbtemp_mapping_start)
ENTRY(clear_page_alias)
- entry a1, 32
+ abi_entry_default
/* Skip setting up a temporary DTLB if not aliased low page. */
@@ -144,14 +144,14 @@ ENTRY(clear_page_alias)
__endla a2, a7, 32
bnez a6, 1f
- retw
+ abi_ret_default
/* We need to invalidate the temporary idtlb entry, if any. */
1: idtlb a4
dsync
- retw
+ abi_ret_default
ENDPROC(clear_page_alias)
@@ -164,7 +164,7 @@ ENDPROC(clear_page_alias)
ENTRY(copy_page_alias)
- entry a1, 32
+ abi_entry_default
/* Skip setting up a temporary DTLB for destination if not aliased. */
@@ -221,19 +221,19 @@ ENTRY(copy_page_alias)
bnez a6, 1f
bnez a7, 2f
- retw
+ abi_ret_default
1: addi a2, a2, -PAGE_SIZE
idtlb a2
dsync
bnez a7, 2f
- retw
+ abi_ret_default
2: addi a3, a3, -PAGE_SIZE+1
idtlb a3
dsync
- retw
+ abi_ret_default
ENDPROC(copy_page_alias)
@@ -248,7 +248,7 @@ ENDPROC(copy_page_alias)
ENTRY(__flush_invalidate_dcache_page_alias)
- entry sp, 16
+ abi_entry_default
movi a7, 0 # required for exception handler
addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE)
@@ -261,7 +261,7 @@ ENTRY(__flush_invalidate_dcache_page_alias)
idtlb a4
dsync
- retw
+ abi_ret_default
ENDPROC(__flush_invalidate_dcache_page_alias)
@@ -272,7 +272,7 @@ ENDPROC(__flush_invalidate_dcache_page_alias)
ENTRY(__invalidate_dcache_page_alias)
- entry sp, 16
+ abi_entry_default
movi a7, 0 # required for exception handler
addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE)
@@ -285,7 +285,7 @@ ENTRY(__invalidate_dcache_page_alias)
idtlb a4
dsync
- retw
+ abi_ret_default
ENDPROC(__invalidate_dcache_page_alias)
#endif
@@ -296,7 +296,7 @@ ENTRY(__tlbtemp_mapping_itlb)
ENTRY(__invalidate_icache_page_alias)
- entry sp, 16
+ abi_entry_default
addi a6, a3, (PAGE_KERNEL_EXEC | _PAGE_HW_WRITE)
mov a4, a2
@@ -307,7 +307,7 @@ ENTRY(__invalidate_icache_page_alias)
iitlb a4
isync
- retw
+ abi_ret_default
ENDPROC(__invalidate_icache_page_alias)
@@ -325,12 +325,12 @@ ENTRY(__tlbtemp_mapping_end)
ENTRY(__invalidate_icache_page)
- entry sp, 16
+ abi_entry_default
___invalidate_icache_page a2 a3
isync
- retw
+ abi_ret_default
ENDPROC(__invalidate_icache_page)
@@ -340,12 +340,12 @@ ENDPROC(__invalidate_icache_page)
ENTRY(__invalidate_dcache_page)
- entry sp, 16
+ abi_entry_default
___invalidate_dcache_page a2 a3
dsync
- retw
+ abi_ret_default
ENDPROC(__invalidate_dcache_page)
@@ -355,12 +355,12 @@ ENDPROC(__invalidate_dcache_page)
ENTRY(__flush_invalidate_dcache_page)
- entry sp, 16
+ abi_entry_default
___flush_invalidate_dcache_page a2 a3
dsync
- retw
+ abi_ret_default
ENDPROC(__flush_invalidate_dcache_page)
@@ -370,12 +370,12 @@ ENDPROC(__flush_invalidate_dcache_page)
ENTRY(__flush_dcache_page)
- entry sp, 16
+ abi_entry_default
___flush_dcache_page a2 a3
dsync
- retw
+ abi_ret_default
ENDPROC(__flush_dcache_page)
@@ -385,12 +385,12 @@ ENDPROC(__flush_dcache_page)
ENTRY(__invalidate_icache_range)
- entry sp, 16
+ abi_entry_default
___invalidate_icache_range a2 a3 a4
isync
- retw
+ abi_ret_default
ENDPROC(__invalidate_icache_range)
@@ -400,12 +400,12 @@ ENDPROC(__invalidate_icache_range)
ENTRY(__flush_invalidate_dcache_range)
- entry sp, 16
+ abi_entry_default
___flush_invalidate_dcache_range a2 a3 a4
dsync
- retw
+ abi_ret_default
ENDPROC(__flush_invalidate_dcache_range)
@@ -415,12 +415,12 @@ ENDPROC(__flush_invalidate_dcache_range)
ENTRY(__flush_dcache_range)
- entry sp, 16
+ abi_entry_default
___flush_dcache_range a2 a3 a4
dsync
- retw
+ abi_ret_default
ENDPROC(__flush_dcache_range)
@@ -430,11 +430,11 @@ ENDPROC(__flush_dcache_range)
ENTRY(__invalidate_dcache_range)
- entry sp, 16
+ abi_entry_default
___invalidate_dcache_range a2 a3 a4
- retw
+ abi_ret_default
ENDPROC(__invalidate_dcache_range)
@@ -444,12 +444,12 @@ ENDPROC(__invalidate_dcache_range)
ENTRY(__invalidate_icache_all)
- entry sp, 16
+ abi_entry_default
___invalidate_icache_all a2 a3
isync
- retw
+ abi_ret_default
ENDPROC(__invalidate_icache_all)
@@ -459,12 +459,12 @@ ENDPROC(__invalidate_icache_all)
ENTRY(__flush_invalidate_dcache_all)
- entry sp, 16
+ abi_entry_default
___flush_invalidate_dcache_all a2 a3
dsync
- retw
+ abi_ret_default
ENDPROC(__flush_invalidate_dcache_all)
@@ -474,11 +474,11 @@ ENDPROC(__flush_invalidate_dcache_all)
ENTRY(__invalidate_dcache_all)
- entry sp, 16
+ abi_entry_default
___invalidate_dcache_all a2 a3
dsync
- retw
+ abi_ret_default
ENDPROC(__invalidate_dcache_all)