diff options
| author | Max Filippov <jcmvbkbc@gmail.com> | 2017-12-15 16:20:56 -0800 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2017-12-16 22:37:09 -0800 |
| commit | 501c26e82df8d253851b80082778eeb37e4bab5c (patch) | |
| tree | 4e90bb47018a93d1647f8b9f2d9b363cdc86b4d4 /arch/xtensa | |
| parent | f21a79cab3773bc17aa845b7738c7f200778a260 (diff) | |
xtensa: implement early_trap_init
Paging on xtensa architecture requires functioning exception handling
because hardware cannot transparently access page tables that are not
currently mapped by TLB. Exception handling is set up late in the
initialization process, but working paging is needed for KASAN.
Provide early_trap_init that sets up minimal exception handling
sufficient for KASAN to work.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'arch/xtensa')
| -rw-r--r-- | arch/xtensa/include/asm/traps.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/xtensa/include/asm/traps.h b/arch/xtensa/include/asm/traps.h index 5bd197097b77..f5cd7a7e65e0 100644 --- a/arch/xtensa/include/asm/traps.h +++ b/arch/xtensa/include/asm/traps.h @@ -42,6 +42,18 @@ struct exc_table { */ extern void * __init trap_set_handler(int cause, void *handler); extern void do_unhandled(struct pt_regs *regs, unsigned long exccause); +void fast_second_level_miss(void); + +/* Initialize minimal exc_table structure sufficient for basic paging */ +static inline void __init early_trap_init(void) +{ + static struct exc_table exc_table __initdata = { + .fast_kernel_handler[EXCCAUSE_DTLB_MISS] = + fast_second_level_miss, + }; + __asm__ __volatile__("wsr %0, excsave1\n" : : "a" (&exc_table)); +} + void secondary_trap_init(void); static inline void spill_registers(void) |