diff options
| author | James Morse <james.morse@arm.com> | 2022-11-30 17:16:02 +0000 |
|---|---|---|
| committer | Will Deacon <will@kernel.org> | 2022-12-01 15:53:13 +0000 |
| commit | 7b24177c631de0d75fd7473ee75666498faf225e (patch) | |
| tree | d64580de832e4531b077b8c9258f23138b71ebc2 /arch | |
| parent | 5ea1534ec320ffaca144136cca3880877738e6d2 (diff) | |
arm64/sysreg: Standardise naming for ID_MMFR5_EL1
To convert the 32bit id registers to use the sysreg generation, they
must first have a regular pattern, to match the symbols the script
generates.
Ensure symbols for the ID_MMFR5_EL1 register have an _EL1 suffix.
No functional change.
Signed-off-by: James Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20221130171637.718182-4-james.morse@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/include/asm/sysreg.h | 2 | ||||
| -rw-r--r-- | arch/arm64/kernel/cpufeature.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index f7d003b975c5..7a719c9804fc 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -751,7 +751,7 @@ #define ID_MMFR4_EL1_AC2_SHIFT 4 #define ID_MMFR4_EL1_SpecSEI_SHIFT 0 -#define ID_MMFR5_ETS_SHIFT 0 +#define ID_MMFR5_EL1_ETS_SHIFT 0 #define ID_PFR0_DIT_SHIFT 24 #define ID_PFR0_CSV2_SHIFT 16 diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index b04500da4379..29239ea0f139 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -522,7 +522,7 @@ static const struct arm64_ftr_bits ftr_id_isar4[] = { }; static const struct arm64_ftr_bits ftr_id_mmfr5[] = { - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_ETS_SHIFT, 4, 0), + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), ARM64_FTR_END, }; |