diff options
| author | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2022-10-27 00:46:51 -0700 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2022-11-06 21:11:10 -0600 |
| commit | b8f298d4f69d82119ac0d22809a17c80b1f188d1 (patch) | |
| tree | 3f96993d7b648c2d499b48c8d88c8bc337838802 /arch | |
| parent | 1caf66104c02d327a2467a69ab18fb24b44e9715 (diff) | |
arm64: dts: qcom: sc7280: fix codec reset line polarity for CRD 1.0/2.0
The driver for the codec, when resetting the chip, first drives the line
low, and then high. This means that the line is active low. Change the
annotation in the DTS accordingly.
Fixes: f8b4eb64f200 ("arm64: dts: qcom: sc7280: Add wcd9385 codec node for CRD 1.0/2.0 and IDP boards")
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221027074652.1044235-5-dmitry.torokhov@gmail.com
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 4884647a8a95..1ac7c091e03f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -34,7 +34,7 @@ pinctrl-0 = <&wcd_reset_n>; pinctrl-1 = <&wcd_reset_n_sleep>; - reset-gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>; + reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>; qcom,rx-device = <&wcd_rx>; qcom,tx-device = <&wcd_tx>; |