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authorKaixu Xia <xiakaixu@huawei.com>2015-03-30 14:13:39 -0600
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2015-04-03 16:17:03 +0200
commit223437c72ae008094e43199dea93c3a144c4e153 (patch)
treea995f97376f17e00f743f02f6e1aa8328864ad4a /arch
parenta0a500efab41c761a1d1fd919d2e42a3a3545b2e (diff)
coresight: remove the unnecessary configuration coresight-default-sink
The coresight-default-sink configuration option has been removed from the framework. As such remove it from DT and bindings. Signed-off-by: Kaixu Xia <xiakaixu@huawei.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/hip04.dtsi1
-rw-r--r--arch/arm/boot/dts/omap3-beagle-xm.dts1
-rw-r--r--arch/arm/boot/dts/omap3-beagle.dts1
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts1
4 files changed, 0 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi
index 238814596a87..44044f275115 100644
--- a/arch/arm/boot/dts/hip04.dtsi
+++ b/arch/arm/boot/dts/hip04.dtsi
@@ -275,7 +275,6 @@
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0 0xe3c42000 0 0x1000>;
- coresight-default-sink;
clocks = <&clk_375m>;
clock-names = "apb_pclk";
port {
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 25f7b0a22114..8cdca51b6984 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -150,7 +150,6 @@
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0x5401b000 0x1000>;
- coresight-default-sink;
clocks = <&emu_src_ck>;
clock-names = "apb_pclk";
port {
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index c792391ef090..6d4c46be8c39 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -145,7 +145,6 @@
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0x5401b000 0x1000>;
- coresight-default-sink;
clocks = <&emu_src_ck>;
clock-names = "apb_pclk";
port {
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index 33920df03640..7a2aeacd62c0 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -362,7 +362,6 @@
compatible = "arm,coresight-etb10", "arm,primecell";
reg = <0 0x20010000 0 0x1000>;
- coresight-default-sink;
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
port {