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authorThierry Reding <treding@nvidia.com>2014-06-19 13:37:09 +0200
committerThierry Reding <treding@nvidia.com>2014-07-17 15:02:12 +0200
commitce90d32d1377a121b11eefdfb1518aa2726f8d0b (patch)
tree54acbd67f49920f9cd04c5b26591d13f50397fa8 /arch
parentd86b1e8dcb26f38757bfd307478fa45285aac004 (diff)
ARM: tegra: tegra124: Add XUSB pad controller
The device tree node in the SoC file contains only the resources (such as registers, resets, ...) but none of the lane assignment information since that's board specific and belongs in the board file. Tested-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/tegra124.dtsi10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index cc9e7504c2da..3af46d3bfbd5 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -1,6 +1,7 @@
#include <dt-bindings/clock/tegra124-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/pinctrl/pinctrl-tegra.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "skeleton.dtsi"
@@ -494,6 +495,15 @@
status = "disabled";
};
+ padctl: padctl@0,7009f000 {
+ compatible = "nvidia,tegra124-xusb-padctl";
+ reg = <0x0 0x7009f000 0x0 0x1000>;
+ resets = <&tegra_car 142>;
+ reset-names = "padctl";
+
+ #phy-cells = <1>;
+ };
+
sdhci@0,700b0000 {
compatible = "nvidia,tegra124-sdhci";
reg = <0x0 0x700b0000 0x0 0x200>;