diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2014-01-23 18:36:55 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2014-01-23 18:36:55 -0800 |
| commit | f2c73464d7b399cf4e0c601c1c7d7b079080fa52 (patch) | |
| tree | 902decd0c280757075bce5068fee679e0ccc261e /arch | |
| parent | 93abdb7785503c269e73e811f3c7fd23a9243b14 (diff) | |
| parent | 273c2279ca502267fac40bcaecb35942380c429c (diff) | |
Merge tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC cleanups from Olof Johansson:
"This is the branch where we usually queue up cleanup efforts, moving
drivers out of the architecture directory, header file restructuring,
etc. Sometimes they tangle with new development so it's hard to keep
it strictly to cleanups.
Some of the things included in this branch are:
* Atmel SAMA5 conversion to common clock
* Reset framework conversion for tegra platforms
- Some of this depends on tegra clock driver reworks that are shared
with Mike Turquette's clk tree.
* Tegra DMA refactoring, which are shared branches with the DMA tree.
* Removal of some header files on exynos to prepare for
multiplatform"
* tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (169 commits)
ARM: mvebu: move Armada 370/XP specific definitions to armada-370-xp.h
ARM: mvebu: remove prototypes of non-existing functions from common.h
ARM: mvebu: move ARMADA_XP_MAX_CPUS to armada-370-xp.h
serial: sh-sci: Rework baud rate calculation
serial: sh-sci: Compute overrun_bit without using baud rate algo
serial: sh-sci: Remove unused GPIO request code
serial: sh-sci: Move overrun_bit and error_mask fields out of pdata
serial: sh-sci: Support resources passed through platform resources
serial: sh-sci: Don't check IRQ in verify port operation
serial: sh-sci: Set the UPF_FIXED_PORT flag
serial: sh-sci: Remove duplicate interrupt check in verify port op
serial: sh-sci: Simplify baud rate calculation algorithms
serial: sh-sci: Remove baud rate calculation algorithm 5
serial: sh-sci: Sort headers alphabetically
ARM: EXYNOS: Kill exynos_pm_late_initcall()
ARM: EXYNOS: Consolidate selection of PM_GENERIC_DOMAINS for Exynos4
ARM: at91: switch Calao QIL-A9260 board to DT
clk: at91: fix pmc_clk_ids data type attriubte
PM / devfreq: use inclusion <mach/map.h> instead of <plat/map-s5p.h>
ARM: EXYNOS: remove <mach/regs-clock.h> for exynos
...
Diffstat (limited to 'arch')
124 files changed, 1408 insertions, 1676 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0b6d8bf1bc34..dbe173dfa4ae 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -743,7 +743,6 @@ config ARCH_S3C64XX select S3C_DEV_NAND select S3C_GPIO_TRACK select SAMSUNG_ATAGS - select SAMSUNG_GPIOLIB_4BIT select SAMSUNG_WAKEMASK select SAMSUNG_WDT_RESET select USB_ARCH_HAS_OHCI diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d57c1a65b24f..36e0d06d3efa 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -6,6 +6,7 @@ dtb-$(CONFIG_ARCH_AT91) += at91rm9200ek.dtb dtb-$(CONFIG_ARCH_AT91) += mpa1600.dtb # sam9260 dtb-$(CONFIG_ARCH_AT91) += animeo_ip.dtb +dtb-$(CONFIG_ARCH_AT91) += at91-qil_a9260.dtb dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb dtb-$(CONFIG_ARCH_AT91) += ethernut5.dtb dtb-$(CONFIG_ARCH_AT91) += evk-pro3.dtb diff --git a/arch/arm/boot/dts/at91-qil_a9260.dts b/arch/arm/boot/dts/at91-qil_a9260.dts new file mode 100644 index 000000000000..5576ae8786c0 --- /dev/null +++ b/arch/arm/boot/dts/at91-qil_a9260.dts @@ -0,0 +1,185 @@ +/* + * at91-qil_a9260.dts - Device Tree file for Calao QIL A9260 board + * + * Copyright (C) 2011-2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> + * + * Licensed under GPLv2. + */ +/dts-v1/; +#include "at91sam9260.dtsi" +/ { + model = "Calao QIL A9260"; + compatible = "calao,qil-a9260", "atmel,at91sam9260", "atmel,at91sam9"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + reg = <0x20000000 0x4000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock@0 { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + usb1: gadget@fffa4000 { + atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>; + status = "okay"; + }; + + mmc0: mmc@fffa8000 { + pinctrl-0 = < + &pinctrl_mmc0_clk + &pinctrl_mmc0_slot0_cmd_dat0 + &pinctrl_mmc0_slot0_dat1_3>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; + + usart0: serial@fffb0000 { + pinctrl-0 = + <&pinctrl_usart0 + &pinctrl_usart0_rts + &pinctrl_usart0_cts + &pinctrl_usart0_dtr_dsr + &pinctrl_usart0_dcd + &pinctrl_usart0_ri>; + status = "okay"; + }; + + usart1: serial@fffb4000 { + pinctrl-0 = + <&pinctrl_usart1 + &pinctrl_usart1_rts + &pinctrl_usart1_cts>; + status = "okay"; + }; + + usart2: serial@fffb8000 { + pinctrl-0 = + <&pinctrl_usart2 + &pinctrl_usart2_rts + &pinctrl_usart2_cts>; + status = "okay"; + }; + + macb0: ethernet@fffc4000 { + phy-mode = "rmii"; + status = "okay"; + }; + + spi0: spi@fffc8000 { + status = "okay"; + cs-gpios = <&pioA 3 GPIO_ACTIVE_HIGH>; + + m41t94@0 { + compatible = "st,m41t94"; + reg = <0>; + spi-max-frequency = <1000000>; + }; + + }; + + dbgu: serial@fffff200 { + status = "okay"; + }; + + shdwc@fffffd10 { + atmel,wakeup-counter = <10>; + atmel,wakeup-rtt-timer; + }; + }; + + usb0: ohci@00500000 { + num-ports = <2>; + status = "okay"; + }; + + nand0: nand@40000000 { + nand-bus-width = <8>; + nand-ecc-mode = "soft"; + nand-on-flash-bbt; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x20000>; + }; + + barebox@20000 { + label = "barebox"; + reg = <0x20000 0x40000>; + }; + + bareboxenv@60000 { + label = "bareboxenv"; + reg = <0x60000 0x20000>; + }; + + bareboxenv2@80000 { + label = "bareboxenv2"; + reg = <0x80000 0x20000>; + }; + + oftree@a0000 { + label = "oftree"; + reg = <0xa0000 0x20000>; + }; + + kernel@c0000 { + label = "kernel"; + reg = <0xc0000 0x400000>; + }; + + rootfs@4c0000 { + label = "rootfs"; + reg = <0x4c0000 0x7800000>; + }; + + data@7cc0000 { + label = "data"; + reg = <0x7cc0000 0x8340000>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + user_led { + label = "user_led"; + gpios = <&pioB 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + user_pb { + label = "user_pb"; + gpios = <&pioB 10 GPIO_ACTIVE_LOW>; + linux,code = <28>; + gpio-key,wakeup; + }; + }; + + i2c@0 { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 5cdaba4cea86..de9feced9935 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -13,6 +13,7 @@ #include <dt-bindings/pinctrl/at91.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clk/at91.h> / { model = "Atmel SAMA5D3 family SoC"; @@ -56,6 +57,14 @@ reg = <0x20000000 0x8000000>; }; + clocks { + adc_op_clk: adc_op_clk{ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + }; + ahb { compatible = "simple-bus"; #address-cells = <1>; @@ -79,6 +88,8 @@ status = "disabled"; #address-cells = <1>; #size-cells = <0>; + clocks = <&mci0_clk>; + clock-names = "mci_clk"; }; spi0: spi@f0004000 { @@ -92,6 +103,8 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi0>; + clocks = <&spi0_clk>; + clock-names = "spi_clk"; status = "disabled"; }; @@ -101,6 +114,8 @@ interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; + clocks = <&ssc0_clk>; + clock-names = "pclk"; status = "disabled"; }; @@ -108,6 +123,8 @@ compatible = "atmel,at91sam9x5-tcb"; reg = <0xf0010000 0x100>; interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb0_clk>; + clock-names = "t0_clk"; }; i2c0: i2c@f0014000 { @@ -121,6 +138,7 @@ pinctrl-0 = <&pinctrl_i2c0>; #address-cells = <1>; #size-cells = <0>; + clocks = <&twi0_clk>; status = "disabled"; }; @@ -135,6 +153,7 @@ pinctrl-0 = <&pinctrl_i2c1>; #address-cells = <1>; #size-cells = <0>; + clocks = <&twi1_clk>; status = "disabled"; }; @@ -144,6 +163,8 @@ interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; + clocks = <&usart0_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -153,6 +174,8 @@ interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; + clocks = <&usart1_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -174,6 +197,8 @@ status = "disabled"; #address-cells = <1>; #size-cells = <0>; + clocks = <&mci1_clk>; + clock-names = "mci_clk"; }; spi1: spi@f8008000 { @@ -187,6 +212,8 @@ dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; + clocks = <&spi1_clk>; + clock-names = "spi_clk"; status = "disabled"; }; @@ -196,6 +223,8 @@ interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; + clocks = <&ssc1_clk>; + clock-names = "pclk"; status = "disabled"; }; @@ -219,6 +248,9 @@ &pinctrl_adc0_ad10 &pinctrl_adc0_ad11 >; + clocks = <&adc_clk>, + <&adc_op_clk>; + clock-names = "adc_clk", "adc_op_clk"; atmel,adc-channel-base = <0x50>; atmel,adc-channels-used = <0xfff>; atmel,adc-drdy-mask = <0x1000000>; @@ -274,6 +306,7 @@ dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; + clocks = <&twi2_clk>; status = "disabled"; }; @@ -283,6 +316,8 @@ interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; + clocks = <&usart2_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -292,6 +327,8 @@ interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; + clocks = <&usart3_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -318,6 +355,8 @@ reg = <0xffffe600 0x200>; interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; + clocks = <&dma0_clk>; + clock-names = "dma_clk"; }; dma1: dma-controller@ffffe800 { @@ -325,6 +364,8 @@ reg = <0xffffe800 0x200>; interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; #dma-cells = <2>; + clocks = <&dma1_clk>; + clock-names = "dma_clk"; }; ramc0: ramc@ffffea00 { @@ -338,6 +379,8 @@ interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&dbgu_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -626,6 +669,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioA_clk>; }; pioB: gpio@fffff400 { @@ -636,6 +680,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioB_clk>; }; pioC: gpio@fffff600 { @@ -646,6 +691,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioC_clk>; }; pioD: gpio@fffff800 { @@ -656,6 +702,7 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioD_clk>; }; pioE: gpio@fffffa00 { @@ -666,12 +713,334 @@ gpio-controller; interrupt-controller; #interrupt-cells = <2>; + clocks = <&pioE_clk>; }; }; pmc: pmc@fffffc00 { - compatible = "atmel,at91rm9200-pmc"; + compatible = "atmel,sama5d3-pmc"; reg = <0xfffffc00 0x120>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + clk32k: slck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + main: mainck { + compatible = "atmel,at91rm9200-clk-main"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_MOSCS>; + clocks = <&clk32k>; + }; + + plla: pllack { + compatible = "atmel,sama5d3-clk-pll"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_LOCKA>; + clocks = <&main>; + reg = <0>; + atmel,clk-input-range = <8000000 50000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>; + }; + + plladiv: plladivck { + compatible = "atmel,at91sam9x5-clk-plldiv"; + #clock-cells = <0>; + clocks = <&plla>; + }; + + utmi: utmick { + compatible = "atmel,at91sam9x5-clk-utmi"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_LOCKU>; + clocks = <&main>; + }; + + mck: masterck { + compatible = "atmel,at91sam9x5-clk-master"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_MCKRDY>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; + atmel,clk-output-range = <0 166000000>; + atmel,clk-divisors = <1 2 4 3>; + }; + + usb: usbck { + compatible = "atmel,at91sam9x5-clk-usb"; + #clock-cells = <0>; + clocks = <&plladiv>, <&utmi>; + }; + + prog: progck { + compatible = "atmel,at91sam9x5-clk-programmable"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&pmc>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; + + prog0: prog0 { + #clock-cells = <0>; + reg = <0>; + interrupts = <AT91_PMC_PCKRDY(0)>; + }; + + prog1: prog1 { + #clock-cells = <0>; + reg = <1>; + interrupts = <AT91_PMC_PCKRDY(1)>; + }; + + prog2: prog2 { + #clock-cells = <0>; + reg = <2>; + interrupts = <AT91_PMC_PCKRDY(2)>; + }; + }; + + smd: smdclk { + compatible = "atmel,at91sam9x5-clk-smd"; + #clock-cells = <0>; + clocks = <&plladiv>, <&utmi>; + }; + + systemck { + compatible = "atmel,at91rm9200-clk-system"; + #address-cells = <1>; + #size-cells = <0>; + + ddrck: ddrck { + #clock-cells = <0>; + reg = <2>; + clocks = <&mck>; + }; + + smdck: smdck { + #clock-cells = <0>; + reg = <4>; + clocks = <&smd>; + }; + + uhpck: uhpck { + #clock-cells = <0>; + reg = <6>; + clocks = <&usb>; + }; + + udpck: udpck { + #clock-cells = <0>; + reg = <7>; + clocks = <&usb>; + }; + + pck0: pck0 { + #clock-cells = <0>; + reg = <8>; + clocks = <&prog0>; + }; + + pck1: pck1 { + #clock-cells = <0>; + reg = <9>; + clocks = <&prog1>; + }; + + pck2: pck2 { + #clock-cells = <0>; + reg = <10>; + clocks = <&prog2>; + }; + }; + + periphck { + compatible = "atmel,at91sam9x5-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mck>; + + dbgu_clk: dbgu_clk { + #clock-cells = <0>; + reg = <2>; + }; + + pioA_clk: pioA_clk { + #clock-cells = <0>; + reg = <6>; + }; + + pioB_clk: pioB_clk { + #clock-cells = <0>; + reg = <7>; + }; + + pioC_clk: pioC_clk { + #clock-cells = <0>; + reg = <8>; + }; + + pioD_clk: pioD_clk { + #clock-cells = <0>; + reg = <9>; + }; + + pioE_clk: pioE_clk { + #clock-cells = <0>; + reg = <10>; + }; + + usart0_clk: usart0_clk { + #clock-cells = <0>; + reg = <12>; + atmel,clk-output-range = <0 66000000>; + }; + + usart1_clk: usart1_clk { + #clock-cells = <0>; + reg = <13>; + atmel,clk-output-range = <0 66000000>; + }; + + usart2_clk: usart2_clk { + #clock-cells = <0>; + reg = <14>; + atmel,clk-output-range = <0 66000000>; + }; + + usart3_clk: usart3_clk { + #clock-cells = <0>; + reg = <15>; + atmel,clk-output-range = <0 66000000>; + }; + + twi0_clk: twi0_clk { + reg = <18>; + #clock-cells = <0>; + atmel,clk-output-range = <0 16625000>; + }; + + twi1_clk: twi1_clk { + #clock-cells = <0>; + reg = <19>; + atmel,clk-output-range = <0 16625000>; + }; + + twi2_clk: twi2_clk { + #clock-cells = <0>; + reg = <20>; + atmel,clk-output-range = <0 16625000>; + }; + + mci0_clk: mci0_clk { + #clock-cells = <0>; + reg = <21>; + }; + + mci1_clk: mci1_clk { + #clock-cells = <0>; + reg = <22>; + }; + + spi0_clk: spi0_clk { + #clock-cells = <0>; + reg = <24>; + atmel,clk-output-range = <0 133000000>; + }; + + spi1_clk: spi1_clk { + #clock-cells = <0>; + reg = <25>; + atmel,clk-output-range = <0 133000000>; + }; + + tcb0_clk: tcb0_clk { + #clock-cells = <0>; + reg = <26>; + atmel,clk-output-range = <0 133000000>; + }; + + pwm_clk: pwm_clk { + #clock-cells = <0>; + reg = <28>; + }; + + adc_clk: adc_clk { + #clock-cells = <0>; + reg = <29>; + atmel,clk-output-range = <0 66000000>; + }; + + dma0_clk: dma0_clk { + #clock-cells = <0>; + reg = <30>; + }; + + dma1_clk: dma1_clk { + #clock-cells = <0>; + reg = <31>; + }; + + uhphs_clk: uhphs_clk { + #clock-cells = <0>; + reg = <32>; + }; + + udphs_clk: udphs_clk { + #clock-cells = <0>; + reg = <33>; + }; + + isi_clk: isi_clk { + #clock-cells = <0>; + reg = <37>; + }; + + ssc0_clk: ssc0_clk { + #clock-cells = <0>; + reg = <38>; + atmel,clk-output-range = <0 66000000>; + }; + + ssc1_clk: ssc1_clk { + #clock-cells = <0>; + reg = <39>; + atmel,clk-output-range = <0 66000000>; + }; + + sha_clk: sha_clk { + #clock-cells = <0>; + reg = <42>; + }; + + aes_clk: aes_clk { + #clock-cells = <0>; + reg = <43>; + }; + + tdes_clk: tdes_clk { + #clock-cells = <0>; + reg = <44>; + }; + + trng_clk: trng_clk { + #clock-cells = <0>; + reg = <45>; + }; + + fuse_clk: fuse_clk { + #clock-cells = <0>; + reg = <48>; + }; + }; }; rstc@fffffe00 { @@ -683,6 +1052,7 @@ compatible = "atmel,at91sam9260-pit"; reg = <0xfffffe30 0xf>; interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&mck>; }; watchdog@fffffe40 { @@ -705,6 +1075,8 @@ reg = <0x00500000 0x100000 0xf8030000 0x4000>; interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&udphs_clk>, <&utmi>; + clock-names = "pclk", "hclk"; status = "disabled"; ep0 { @@ -817,6 +1189,9 @@ compatible = "atmel,at91rm9200-ohci", "usb-ohci"; reg = <0x00600000 0x100000>; interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>, + <&uhpck>; + clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; status = "disabled"; }; @@ -824,6 +1199,8 @@ compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; reg = <0x00700000 0x100000>; interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&usb>, <&uhphs_clk>, <&uhpck>; + clock-names = "usb_clk", "ehci_clk", "uhpck"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi index 8ed3260cef66..a0775851cce5 100644 --- a/arch/arm/boot/dts/sama5d3_can.dtsi +++ b/arch/arm/boot/dts/sama5d3_can.dtsi @@ -32,12 +32,30 @@ }; + pmc: pmc@fffffc00 { + periphck { + can0_clk: can0_clk { + #clock-cells = <0>; + reg = <40>; + atmel,clk-output-range = <0 66000000>; + }; + + can1_clk: can0_clk { + #clock-cells = <0>; + reg = <41>; + atmel,clk-output-range = <0 66000000>; + }; + }; + }; + can0: can@f000c000 { compatible = "atmel,at91sam9x5-can"; reg = <0xf000c000 0x300>; interrupts = <40 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can0_rx_tx>; + clocks = <&can0_clk>; + clock-names = "can_clk"; status = "disabled"; }; @@ -47,6 +65,8 @@ interrupts = <41 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_rx_tx>; + clocks = <&can1_clk>; + clock-names = "can_clk"; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/sama5d3_emac.dtsi b/arch/arm/boot/dts/sama5d3_emac.dtsi index 4d4f351f1f9f..fe2af9276312 100644 --- a/arch/arm/boot/dts/sama5d3_emac.dtsi +++ b/arch/arm/boot/dts/sama5d3_emac.dtsi @@ -31,12 +31,23 @@ }; }; + pmc: pmc@fffffc00 { + periphck { + macb1_clk: macb1_clk { + #clock-cells = <0>; + reg = <35>; + }; + }; + }; + macb1: ethernet@f802c000 { compatible = "cdns,at32ap7000-macb", "cdns,macb"; reg = <0xf802c000 0x100>; interrupts = <35 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb1_rmii>; + clocks = <&macb1_clk>, <&macb1_clk>; + clock-names = "hclk", "pclk"; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/sama5d3_gmac.dtsi b/arch/arm/boot/dts/sama5d3_gmac.dtsi index 0ba8be30ccd8..a6cb0508762f 100644 --- a/arch/arm/boot/dts/sama5d3_gmac.dtsi +++ b/arch/arm/boot/dts/sama5d3_gmac.dtsi @@ -64,12 +64,23 @@ }; }; + pmc: pmc@fffffc00 { + periphck { + macb0_clk: macb0_clk { + #clock-cells = <0>; + reg = <34>; + }; + }; + }; + macb0: ethernet@f0028000 { compatible = "cdns,pc302-gem", "cdns,gem"; reg = <0xf0028000 0x100>; interrupts = <34 IRQ_TYPE_LEVEL_HIGH 3>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_macb0_data_rgmii &pinctrl_macb0_signal_rgmii>; + clocks = <&macb0_clk>, <&macb0_clk>; + clock-names = "hclk", "pclk"; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/sama5d3_lcd.dtsi b/arch/arm/boot/dts/sama5d3_lcd.dtsi index 01f52a79f8ba..85d302701565 100644 --- a/arch/arm/boot/dts/sama5d3_lcd.dtsi +++ b/arch/arm/boot/dts/sama5d3_lcd.dtsi @@ -50,6 +50,23 @@ }; }; }; + + pmc: pmc@fffffc00 { + periphck { + lcdc_clk: lcdc_clk { + #clock-cells = <0>; + reg = <36>; + }; + }; + + systemck { + lcdck: lcdck { + #clock-cells = <0>; + reg = <3>; + clocks = <&mck>; + }; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/sama5d3_mci2.dtsi b/arch/arm/boot/dts/sama5d3_mci2.dtsi index 38e88e39e551..b029fe7ef17a 100644 --- a/arch/arm/boot/dts/sama5d3_mci2.dtsi +++ b/arch/arm/boot/dts/sama5d3_mci2.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/pinctrl/at91.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/clk/at91.h> / { ahb { @@ -30,6 +31,15 @@ }; }; + pmc: pmc@fffffc00 { + periphck { + mci2_clk: mci2_clk { + #clock-cells = <0>; + reg = <23>; + }; + }; + }; + mmc2: mmc@f8004000 { compatible = "atmel,hsmci"; reg = <0xf8004000 0x600>; @@ -38,6 +48,8 @@ dma-names = "rxtx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mmc2_clk_cmd_dat0 &pinctrl_mmc2_dat1_3>; + clocks = <&mci2_clk>; + clock-names = "mci_clk"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi index 5264bb4a6998..382b04431f66 100644 --- a/arch/arm/boot/dts/sama5d3_tcb1.dtsi +++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/pinctrl/at91.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/clk/at91.h> / { aliases { @@ -17,10 +18,21 @@ ahb { apb { + pmc: pmc@fffffc00 { + periphck { + tcb1_clk: tcb1_clk { + #clock-cells = <0>; + reg = <27>; + }; + }; + }; + tcb1: timer@f8014000 { compatible = "atmel,at91sam9x5-tcb"; reg = <0xf8014000 0x100>; interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb1_clk>; + clock-names = "t0_clk"; }; }; }; diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi index 98fcb2d57446..49d4d76ca6f4 100644 --- a/arch/arm/boot/dts/sama5d3_uart.dtsi +++ b/arch/arm/boot/dts/sama5d3_uart.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/pinctrl/at91.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/clk/at91.h> / { ahb { @@ -31,12 +32,30 @@ }; }; + pmc: pmc@fffffc00 { + periphck { + uart0_clk: uart0_clk { + #clock-cells = <0>; + reg = <16>; + atmel,clk-output-range = <0 66000000>; + }; + + uart1_clk: uart1_clk { + #clock-cells = <0>; + reg = <17>; + atmel,clk-output-range = <0 66000000>; + }; + }; + }; + uart0: serial@f0024000 { compatible = "atmel,at91sam9260-usart"; reg = <0xf0024000 0x200>; interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; + clocks = <&uart0_clk>; + clock-names = "usart"; status = "disabled"; }; @@ -46,6 +65,8 @@ interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; + clocks = <&uart1_clk>; + clock-names = "usart"; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi index 726a0f35100c..f55ed072c8e6 100644 --- a/arch/arm/boot/dts/sama5d3xcm.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi @@ -18,17 +18,6 @@ reg = <0x20000000 0x20000000>; }; - clocks { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - main_clock: clock@0 { - compatible = "atmel,osc", "fixed-clock"; - clock-frequency = <12000000>; - }; - }; - ahb { apb { spi0: spi@f0004000 { @@ -38,6 +27,12 @@ macb0: ethernet@f0028000 { phy-mode = "rgmii"; }; + + pmc: pmc@fffffc00 { + main: mainck { + clock-frequency = <12000000>; + }; + }; }; nand0: nand@60000000 { diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 8d42787c8ff1..731249fbe206 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -43,6 +43,7 @@ compatible = "nvidia,tegra114-car"; reg = <0x60006000 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; apbdma: dma { @@ -81,6 +82,9 @@ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_APBDMA>; + resets = <&tegra_car 34>; + reset-names = "dma"; + #dma-cells = <1>; }; ahb: ahb { @@ -124,9 +128,12 @@ reg = <0x70006000 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 8>; - status = "disabled"; clocks = <&tegra_car TEGRA114_CLK_UARTA>; + resets = <&tegra_car 6>; + reset-names = "serial"; + dmas = <&apbdma 8>, <&apbdma 8>; + dma-names = "rx", "tx"; + status = "disabled"; }; uartb: serial@70006040 { @@ -134,9 +141,12 @@ reg = <0x70006040 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 9>; - status = "disabled"; clocks = <&tegra_car TEGRA114_CLK_UARTB>; + resets = <&tegra_car 7>; + reset-names = "serial"; + dmas = <&apbdma 9>, <&apbdma 9>; + dma-names = "rx", "tx"; + status = "disabled"; }; uartc: serial@70006200 { @@ -144,9 +154,12 @@ reg = <0x70006200 0x100>; reg-shift = <2>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 10>; - status = "disabled"; clocks = <&tegra_car TEGRA114_CLK_UARTC>; + resets = <&tegra_car 55>; + reset-names = "serial"; + dmas = <&apbdma 10>, <&apbdma 10>; + dma-names = "rx", "tx"; + status = "disabled"; }; uartd: serial@70006300 { @@ -154,9 +167,12 @@ reg = <0x70006300 0x100>; reg-shift = <2>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 19>; - status = "disabled"; clocks = <&tegra_car TEGRA114_CLK_UARTD>; + resets = <&tegra_car 65>; + reset-names = "serial"; + dmas = <&apbdma 19>, <&apbdma 19>; + dma-names = "rx", "tx"; + status = "disabled"; }; pwm: pwm { @@ -164,6 +180,8 @@ reg = <0x7000a000 0x100>; #pwm-cells = <2>; clocks = <&tegra_car TEGRA114_CLK_PWM>; + resets = <&tegra_car 17>; + reset-names = "pwm"; status = "disabled"; }; @@ -175,6 +193,10 @@ #size-cells = <0>; clocks = <&tegra_car TEGRA114_CLK_I2C1>; clock-names = "div-clk"; + resets = <&tegra_car 12>; + reset-names = "i2c"; + dmas = <&apbdma 21>, <&apbdma 21>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -186,6 +208,10 @@ #size-cells = <0>; clocks = <&tegra_car TEGRA114_CLK_I2C2>; clock-names = "div-clk"; + resets = <&tegra_car 54>; + reset-names = "i2c"; + dmas = <&apbdma 22>, <&apbdma 22>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -197,6 +223,10 @@ #size-cells = <0>; clocks = <&tegra_car TEGRA114_CLK_I2C3>; clock-names = "div-clk"; + resets = <&tegra_car 67>; + reset-names = "i2c"; + dmas = <&apbdma 23>, <&apbdma 23>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -208,6 +238,10 @@ #size-cells = <0>; clocks = <&tegra_car TEGRA114_CLK_I2C4>; clock-names = "div-clk"; + resets = <&tegra_car 103>; + reset-names = "i2c"; + dmas = <&apbdma 26>, <&apbdma 26>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -219,6 +253,10 @@ #size-cells = <0>; clocks = <&tegra_car TEGRA114_CLK_I2C5>; clock-names = "div-clk"; + resets = <&tegra_car 47>; + reset-names = "i2c"; + dmas = <&apbdma 24>, <&apbdma 24>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -226,11 +264,14 @@ compatible = "nvidia,tegra114-spi"; reg = <0x7000d400 0x200>; interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 15>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA114_CLK_SBC1>; clock-names = "spi"; + resets = <&tegra_car 41>; + reset-names = "spi"; + dmas = <&apbdma 15>, <&apbdma 15>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -238,11 +279,14 @@ compatible = "nvidia,tegra114-spi"; reg = <0x7000d600 0x200>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 16>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA114_CLK_SBC2>; clock-names = "spi"; + resets = <&tegra_car 44>; + reset-names = "spi"; + dmas = <&apbdma 16>, <&apbdma 16>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -250,11 +294,14 @@ compatible = "nvidia,tegra114-spi"; reg = <0x7000d800 0x200>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 17>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA114_CLK_SBC3>; clock-names = "spi"; + resets = <&tegra_car 46>; + reset-names = "spi"; + dmas = <&apbdma 17>, <&apbdma 17>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -262,11 +309,14 @@ compatible = "nvidia,tegra114-spi"; reg = <0x7000da00 0x200>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 18>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA114_CLK_SBC4>; clock-names = "spi"; + resets = <&tegra_car 68>; + reset-names = "spi"; + dmas = <&apbdma 18>, <&apbdma 18>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -274,11 +324,14 @@ compatible = "nvidia,tegra114-spi"; reg = <0x7000dc00 0x200>; interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 27>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA114_CLK_SBC5>; clock-names = "spi"; + resets = <&tegra_car 104>; + reset-names = "spi"; + dmas = <&apbdma 27>, <&apbdma 27>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -286,11 +339,14 @@ compatible = "nvidia,tegra114-spi"; reg = <0x7000de00 0x200>; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 28>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA114_CLK_SBC6>; clock-names = "spi"; + resets = <&tegra_car 105>; + reset-names = "spi"; + dmas = <&apbdma 28>, <&apbdma 28>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -306,6 +362,8 @@ reg = <0x7000e200 0x100>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_KBC>; + resets = <&tegra_car 36>; + reset-names = "kbc"; status = "disabled"; }; @@ -333,26 +391,39 @@ <0x70080200 0x100>, <0x70081000 0x200>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 1>, <&apbdma 2>, - <&apbdma 3>, <&apbdma 4>, <&apbdma 6>, <&apbdma 7>, - <&apbdma 12>, <&apbdma 13>, <&apbdma 14>, - <&apbdma 29>; clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>, - <&tegra_car TEGRA114_CLK_APBIF>, - <&tegra_car TEGRA114_CLK_I2S0>, - <&tegra_car TEGRA114_CLK_I2S1>, - <&tegra_car TEGRA114_CLK_I2S2>, - <&tegra_car TEGRA114_CLK_I2S3>, - <&tegra_car TEGRA114_CLK_I2S4>, - <&tegra_car TEGRA114_CLK_DAM0>, - <&tegra_car TEGRA114_CLK_DAM1>, - <&tegra_car TEGRA114_CLK_DAM2>, - <&tegra_car TEGRA114_CLK_SPDIF_IN>, - <&tegra_car TEGRA114_CLK_AMX>, - <&tegra_car TEGRA114_CLK_ADX>; - clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", + <&tegra_car TEGRA114_CLK_APBIF>; + clock-names = "d_audio", "apbif"; + resets = <&tegra_car 106>, /* d_audio */ + <&tegra_car 107>, /* apbif */ + <&tegra_car 30>, /* i2s0 */ + <&tegra_car 11>, /* i2s1 */ + <&tegra_car 18>, /* i2s2 */ + <&tegra_car 101>, /* i2s3 */ + <&tegra_car 102>, /* i2s4 */ + <&tegra_car 108>, /* dam0 */ + <&tegra_car 109>, /* dam1 */ + <&tegra_car 110>, /* dam2 */ + <&tegra_car 10>, /* spdif */ + <&tegra_car 153>, /* amx */ + <&tegra_car 154>; /* adx */ + reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", "i2s3", "i2s4", "dam0", "dam1", "dam2", - "spdif_in", "amx", "adx"; + "spdif", "amx", "adx"; + dmas = <&apbdma 1>, <&apbdma 1>, + <&apbdma 2>, <&apbdma 2>, + <&apbdma 3>, <&apbdma 3>, + <&apbdma 4>, <&apbdma 4>, + <&apbdma 6>, <&apbdma 6>, + <&apbdma 7>, <&apbdma 7>, + <&apbdma 12>, <&apbdma 12>, + <&apbdma 13>, <&apbdma 13>, + <&apbdma 14>, <&apbdma 14>, + <&apbdma 29>, <&apbdma 29>; + dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", + "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", + "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", + "rx9", "tx9"; ranges; #address-cells = <1>; #size-cells = <1>; @@ -362,6 +433,8 @@ reg = <0x70080300 0x100>; nvidia,ahub-cif-ids = <4 4>; clocks = <&tegra_car TEGRA114_CLK_I2S0>; + resets = <&tegra_car 30>; + reset-names = "i2s"; status = "disabled"; }; @@ -370,6 +443,8 @@ reg = <0x70080400 0x100>; nvidia,ahub-cif-ids = <5 5>; clocks = <&tegra_car TEGRA114_CLK_I2S1>; + resets = <&tegra_car 11>; + reset-names = "i2s"; status = "disabled"; }; @@ -378,6 +453,8 @@ reg = <0x70080500 0x100>; nvidia,ahub-cif-ids = <6 6>; clocks = <&tegra_car TEGRA114_CLK_I2S2>; + resets = <&tegra_car 18>; + reset-names = "i2s"; status = "disabled"; }; @@ -386,6 +463,8 @@ reg = <0x70080600 0x100>; nvidia,ahub-cif-ids = <7 7>; clocks = <&tegra_car TEGRA114_CLK_I2S3>; + resets = <&tegra_car 101>; + reset-names = "i2s"; status = "disabled"; }; @@ -394,6 +473,8 @@ reg = <0x70080700 0x100>; nvidia,ahub-cif-ids = <8 8>; clocks = <&tegra_car TEGRA114_CLK_I2S4>; + resets = <&tegra_car 102>; + reset-names = "i2s"; status = "disabled"; }; }; @@ -403,6 +484,8 @@ reg = <0x78000000 0x200>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; + resets = <&tegra_car 14>; + reset-names = "sdhci"; status = "disable"; }; @@ -411,6 +494,8 @@ reg = <0x78000200 0x200>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; + resets = <&tegra_car 9>; + reset-names = "sdhci"; status = "disable"; }; @@ -419,6 +504,8 @@ reg = <0x78000400 0x200>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; + resets = <&tegra_car 69>; + reset-names = "sdhci"; status = "disable"; }; @@ -427,6 +514,8 @@ reg = <0x78000600 0x200>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; + resets = <&tegra_car 15>; + reset-names = "sdhci"; status = "disable"; }; @@ -436,6 +525,8 @@ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; phy_type = "utmi"; clocks = <&tegra_car TEGRA114_CLK_USBD>; + resets = <&tegra_car 22>; + reset-names = "usb"; nvidia,phy = <&phy1>; status = "disabled"; }; @@ -467,6 +558,8 @@ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; phy_type = "utmi"; clocks = <&tegra_car TEGRA114_CLK_USB3>; + resets = <&tegra_car 59>; + reset-names = "usb"; nvidia,phy = <&phy3>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 8d71fc9d8a2f..e57fb3aefc2a 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -280,6 +280,8 @@ clocks = <&tegra_car TEGRA20_CLK_I2C3>, <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 67>; + reset-names = "i2c"; }; i2c@7000d000 { diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index df40b54fd8bc..c90d0aac3afe 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -22,6 +22,8 @@ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ clocks = <&tegra_car TEGRA20_CLK_HOST1X>; + resets = <&tegra_car 28>; + reset-names = "host1x"; #address-cells = <1>; #size-cells = <1>; @@ -33,6 +35,8 @@ reg = <0x54040000 0x00040000>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_MPE>; + resets = <&tegra_car 60>; + reset-names = "mpe"; }; vi { @@ -40,6 +44,8 @@ reg = <0x54080000 0x00040000>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_VI>; + resets = <&tegra_car 20>; + reset-names = "vi"; }; epp { @@ -47,6 +53,8 @@ reg = <0x540c0000 0x00040000>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_EPP>; + resets = <&tegra_car 19>; + reset-names = "epp"; }; isp { @@ -54,6 +62,8 @@ reg = <0x54100000 0x00040000>; interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_ISP>; + resets = <&tegra_car 23>; + reset-names = "isp"; }; gr2d { @@ -61,12 +71,16 @@ reg = <0x54140000 0x00040000>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_GR2D>; + resets = <&tegra_car 21>; + reset-names = "2d"; }; gr3d { compatible = "nvidia,tegra20-gr3d"; reg = <0x54180000 0x00040000>; clocks = <&tegra_car TEGRA20_CLK_GR3D>; + resets = <&tegra_car 24>; + reset-names = "3d"; }; dc@54200000 { @@ -75,7 +89,9 @@ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_DISP1>, <&tegra_car TEGRA20_CLK_PLL_P>; - clock-names = "disp1", "parent"; + clock-names = "dc", "parent"; + resets = <&tegra_car 27>; + reset-names = "dc"; rgb { status = "disabled"; @@ -88,7 +104,9 @@ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_DISP2>, <&tegra_car TEGRA20_CLK_PLL_P>; - clock-names = "disp2", "parent"; + clock-names = "dc", "parent"; + resets = <&tegra_car 26>; + reset-names = "dc"; rgb { status = "disabled"; @@ -102,6 +120,8 @@ clocks = <&tegra_car TEGRA20_CLK_HDMI>, <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; clock-names = "hdmi", "parent"; + resets = <&tegra_car 51>; + reset-names = "hdmi"; status = "disabled"; }; @@ -117,6 +137,8 @@ compatible = "nvidia,tegra20-dsi"; reg = <0x54300000 0x00040000>; clocks = <&tegra_car TEGRA20_CLK_DSI>; + resets = <&tegra_car 48>; + reset-names = "dsi"; status = "disabled"; }; }; @@ -160,6 +182,7 @@ compatible = "nvidia,tegra20-car"; reg = <0x60006000 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; apbdma: dma { @@ -182,6 +205,9 @@ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_APBDMA>; + resets = <&tegra_car 34>; + reset-names = "dma"; + #dma-cells = <1>; }; ahb { @@ -222,8 +248,11 @@ compatible = "nvidia,tegra20-ac97"; reg = <0x70002000 0x200>; interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 12>; clocks = <&tegra_car TEGRA20_CLK_AC97>; + resets = <&tegra_car 3>; + reset-names = "ac97"; + dmas = <&apbdma 12>, <&apbdma 12>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -231,8 +260,11 @@ compatible = "nvidia,tegra20-i2s"; reg = <0x70002800 0x200>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 2>; clocks = <&tegra_car TEGRA20_CLK_I2S1>; + resets = <&tegra_car 11>; + reset-names = "i2s"; + dmas = <&apbdma 2>, <&apbdma 2>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -240,8 +272,11 @@ compatible = "nvidia,tegra20-i2s"; reg = <0x70002a00 0x200>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 1>; clocks = <&tegra_car TEGRA20_CLK_I2S2>; + resets = <&tegra_car 18>; + reset-names = "i2s"; + dmas = <&apbdma 1>, <&apbdma 1>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -257,8 +292,11 @@ reg = <0x70006000 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 8>; clocks = <&tegra_car TEGRA20_CLK_UARTA>; + resets = <&tegra_car 6>; + reset-names = "serial"; + dmas = <&apbdma 8>, <&apbdma 8>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -267,8 +305,11 @@ reg = <0x70006040 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 9>; clocks = <&tegra_car TEGRA20_CLK_UARTB>; + resets = <&tegra_car 7>; + reset-names = "serial"; + dmas = <&apbdma 9>, <&apbdma 9>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -277,8 +318,11 @@ reg = <0x70006200 0x100>; reg-shift = <2>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 10>; clocks = <&tegra_car TEGRA20_CLK_UARTC>; + resets = <&tegra_car 55>; + reset-names = "serial"; + dmas = <&apbdma 10>, <&apbdma 10>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -287,8 +331,11 @@ reg = <0x70006300 0x100>; reg-shift = <2>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 19>; clocks = <&tegra_car TEGRA20_CLK_UARTD>; + resets = <&tegra_car 65>; + reset-names = "serial"; + dmas = <&apbdma 19>, <&apbdma 19>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -297,8 +344,11 @@ reg = <0x70006400 0x100>; reg-shift = <2>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 20>; clocks = <&tegra_car TEGRA20_CLK_UARTE>; + resets = <&tegra_car 66>; + reset-names = "serial"; + dmas = <&apbdma 20>, <&apbdma 20>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -307,6 +357,8 @@ reg = <0x7000a000 0x100>; #pwm-cells = <2>; clocks = <&tegra_car TEGRA20_CLK_PWM>; + resets = <&tegra_car 17>; + reset-names = "pwm"; status = "disabled"; }; @@ -326,6 +378,10 @@ clocks = <&tegra_car TEGRA20_CLK_I2C1>, <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 12>; + reset-names = "i2c"; + dmas = <&apbdma 21>, <&apbdma 21>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -333,10 +389,13 @@ compatible = "nvidia,tegra20-sflash"; reg = <0x7000c380 0x80>; interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 11>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA20_CLK_SPI>; + resets = <&tegra_car 43>; + reset-names = "spi"; + dmas = <&apbdma 11>, <&apbdma 11>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -349,6 +408,10 @@ clocks = <&tegra_car TEGRA20_CLK_I2C2>, <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 54>; + reset-names = "i2c"; + dmas = <&apbdma 22>, <&apbdma 22>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -361,6 +424,10 @@ clocks = <&tegra_car TEGRA20_CLK_I2C3>, <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 67>; + reset-names = "i2c"; + dmas = <&apbdma 23>, <&apbdma 23>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -373,6 +440,10 @@ clocks = <&tegra_car TEGRA20_CLK_DVC>, <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 47>; + reset-names = "i2c"; + dmas = <&apbdma 24>, <&apbdma 24>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -380,10 +451,13 @@ compatible = "nvidia,tegra20-slink"; reg = <0x7000d400 0x200>; interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 15>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA20_CLK_SBC1>; + resets = <&tegra_car 41>; + reset-names = "spi"; + dmas = <&apbdma 15>, <&apbdma 15>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -391,10 +465,13 @@ compatible = "nvidia,tegra20-slink"; reg = <0x7000d600 0x200>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 16>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA20_CLK_SBC2>; + resets = <&tegra_car 44>; + reset-names = "spi"; + dmas = <&apbdma 16>, <&apbdma 16>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -402,10 +479,13 @@ compatible = "nvidia,tegra20-slink"; reg = <0x7000d800 0x200>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 17>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA20_CLK_SBC3>; + resets = <&tegra_car 46>; + reset-names = "spi"; + dmas = <&apbdma 17>, <&apbdma 17>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -413,10 +493,13 @@ compatible = "nvidia,tegra20-slink"; reg = <0x7000da00 0x200>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 18>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA20_CLK_SBC4>; + resets = <&tegra_car 68>; + reset-names = "spi"; + dmas = <&apbdma 18>, <&apbdma 18>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -425,6 +508,8 @@ reg = <0x7000e200 0x100>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_KBC>; + resets = <&tegra_car 36>; + reset-names = "kbc"; status = "disabled"; }; @@ -478,9 +563,12 @@ clocks = <&tegra_car TEGRA20_CLK_PEX>, <&tegra_car TEGRA20_CLK_AFI>, - <&tegra_car TEGRA20_CLK_PCIE_XCLK>, <&tegra_car TEGRA20_CLK_PLL_E>; - clock-names = "pex", "afi", "pcie_xclk", "pll_e"; + clock-names = "pex", "afi", "pll_e"; + resets = <&tegra_car 70>, + <&tegra_car 72>, + <&tegra_car 74>; + reset-names = "pex", "afi", "pcie_x"; status = "disabled"; pci@1,0 { @@ -517,6 +605,8 @@ phy_type = "utmi"; nvidia,has-legacy-mode; clocks = <&tegra_car TEGRA20_CLK_USBD>; + resets = <&tegra_car 22>; + reset-names = "usb"; nvidia,needs-double-reset; nvidia,phy = <&phy1>; status = "disabled"; @@ -548,6 +638,8 @@ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; phy_type = "ulpi"; clocks = <&tegra_car TEGRA20_CLK_USB2>; + resets = <&tegra_car 58>; + reset-names = "usb"; nvidia,phy = <&phy2>; status = "disabled"; }; @@ -569,6 +661,8 @@ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; phy_type = "utmi"; clocks = <&tegra_car TEGRA20_CLK_USB3>; + resets = <&tegra_car 59>; + reset-names = "usb"; nvidia,phy = <&phy3>; status = "disabled"; }; @@ -597,6 +691,8 @@ reg = <0xc8000000 0x200>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; + resets = <&tegra_car 14>; + reset-names = "sdhci"; status = "disabled"; }; @@ -605,6 +701,8 @@ reg = <0xc8000200 0x200>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; + resets = <&tegra_car 9>; + reset-names = "sdhci"; status = "disabled"; }; @@ -613,6 +711,8 @@ reg = <0xc8000400 0x200>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; + resets = <&tegra_car 69>; + reset-names = "sdhci"; status = "disabled"; }; @@ -621,6 +721,8 @@ reg = <0xc8000600 0x200>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; + resets = <&tegra_car 15>; + reset-names = "sdhci"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 2bd55cfd88ad..31259b09e7cc 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -40,10 +40,13 @@ clocks = <&tegra_car TEGRA30_CLK_PCIE>, <&tegra_car TEGRA30_CLK_AFI>, - <&tegra_car TEGRA30_CLK_PCIEX>, <&tegra_car TEGRA30_CLK_PLL_E>, <&tegra_car TEGRA30_CLK_CML0>; - clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml"; + clock-names = "pex", "afi", "pll_e", "cml"; + resets = <&tegra_car 70>, + <&tegra_car 72>, + <&tegra_car 74>; + reset-names = "pex", "afi", "pcie_x"; status = "disabled"; pci@1,0 { @@ -92,6 +95,8 @@ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ clocks = <&tegra_car TEGRA30_CLK_HOST1X>; + resets = <&tegra_car 28>; + reset-names = "host1x"; #address-cells = <1>; #size-cells = <1>; @@ -103,6 +108,8 @@ reg = <0x54040000 0x00040000>; interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_MPE>; + resets = <&tegra_car 60>; + reset-names = "mpe"; }; vi { @@ -110,6 +117,8 @@ reg = <0x54080000 0x00040000>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_VI>; + resets = <&tegra_car 20>; + reset-names = "vi"; }; epp { @@ -117,6 +126,8 @@ reg = <0x540c0000 0x00040000>; interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_EPP>; + resets = <&tegra_car 19>; + reset-names = "epp"; }; isp { @@ -124,12 +135,16 @@ reg = <0x54100000 0x00040000>; interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_ISP>; + resets = <&tegra_car 23>; + reset-names = "isp"; }; gr2d { compatible = "nvidia,tegra30-gr2d"; reg = <0x54140000 0x00040000>; interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + resets = <&tegra_car 21>; + reset-names = "2d"; clocks = <&tegra_car TEGRA30_CLK_GR2D>; }; @@ -139,6 +154,9 @@ clocks = <&tegra_car TEGRA30_CLK_GR3D &tegra_car TEGRA30_CLK_GR3D2>; clock-names = "3d", "3d2"; + resets = <&tegra_car 24>, + <&tegra_car 98>; + reset-names = "3d", "3d2"; }; dc@54200000 { @@ -147,7 +165,9 @@ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_DISP1>, <&tegra_car TEGRA30_CLK_PLL_P>; - clock-names = "disp1", "parent"; + clock-names = "dc", "parent"; + resets = <&tegra_car 27>; + reset-names = "dc"; rgb { status = "disabled"; @@ -160,7 +180,9 @@ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_DISP2>, <&tegra_car TEGRA30_CLK_PLL_P>; - clock-names = "disp2", "parent"; + clock-names = "dc", "parent"; + resets = <&tegra_car 26>; + reset-names = "dc"; rgb { status = "disabled"; @@ -174,6 +196,8 @@ clocks = <&tegra_car TEGRA30_CLK_HDMI>, <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>; clock-names = "hdmi", "parent"; + resets = <&tegra_car 51>; + reset-names = "hdmi"; status = "disabled"; }; @@ -189,6 +213,8 @@ compatible = "nvidia,tegra30-dsi"; reg = <0x54300000 0x00040000>; clocks = <&tegra_car TEGRA30_CLK_DSIA>; + resets = <&tegra_car 48>; + reset-names = "dsi"; status = "disabled"; }; }; @@ -234,6 +260,7 @@ compatible = "nvidia,tegra30-car"; reg = <0x60006000 0x1000>; #clock-cells = <1>; + #reset-cells = <1>; }; apbdma: dma { @@ -272,6 +299,9 @@ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_APBDMA>; + resets = <&tegra_car 34>; + reset-names = "dma"; + #dma-cells = <1>; }; ahb: ahb { @@ -315,8 +345,11 @@ reg = <0x70006000 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 8>; clocks = <&tegra_car TEGRA30_CLK_UARTA>; + resets = <&tegra_car 6>; + reset-names = "serial"; + dmas = <&apbdma 8>, <&apbdma 8>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -325,8 +358,11 @@ reg = <0x70006040 0x40>; reg-shift = <2>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 9>; clocks = <&tegra_car TEGRA30_CLK_UARTB>; + resets = <&tegra_car 7>; + reset-names = "serial"; + dmas = <&apbdma 9>, <&apbdma 9>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -335,8 +371,11 @@ reg = <0x70006200 0x100>; reg-shift = <2>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 10>; clocks = <&tegra_car TEGRA30_CLK_UARTC>; + resets = <&tegra_car 55>; + reset-names = "serial"; + dmas = <&apbdma 10>, <&apbdma 10>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -345,8 +384,11 @@ reg = <0x70006300 0x100>; reg-shift = <2>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 19>; clocks = <&tegra_car TEGRA30_CLK_UARTD>; + resets = <&tegra_car 65>; + reset-names = "serial"; + dmas = <&apbdma 19>, <&apbdma 19>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -355,8 +397,11 @@ reg = <0x70006400 0x100>; reg-shift = <2>; interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 20>; clocks = <&tegra_car TEGRA30_CLK_UARTE>; + resets = <&tegra_car 66>; + reset-names = "serial"; + dmas = <&apbdma 20>, <&apbdma 20>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -365,6 +410,8 @@ reg = <0x7000a000 0x100>; #pwm-cells = <2>; clocks = <&tegra_car TEGRA30_CLK_PWM>; + resets = <&tegra_car 17>; + reset-names = "pwm"; status = "disabled"; }; @@ -384,6 +431,10 @@ clocks = <&tegra_car TEGRA30_CLK_I2C1>, <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 12>; + reset-names = "i2c"; + dmas = <&apbdma 21>, <&apbdma 21>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -396,6 +447,10 @@ clocks = <&tegra_car TEGRA30_CLK_I2C2>, <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 54>; + reset-names = "i2c"; + dmas = <&apbdma 22>, <&apbdma 22>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -408,6 +463,10 @@ clocks = <&tegra_car TEGRA30_CLK_I2C3>, <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 67>; + reset-names = "i2c"; + dmas = <&apbdma 23>, <&apbdma 23>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -419,7 +478,11 @@ #size-cells = <0>; clocks = <&tegra_car TEGRA30_CLK_I2C4>, <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; + resets = <&tegra_car 103>; + reset-names = "i2c"; clock-names = "div-clk", "fast-clk"; + dmas = <&apbdma 26>, <&apbdma 26>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -432,6 +495,10 @@ clocks = <&tegra_car TEGRA30_CLK_I2C5>, <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; clock-names = "div-clk", "fast-clk"; + resets = <&tegra_car 47>; + reset-names = "i2c"; + dmas = <&apbdma 24>, <&apbdma 24>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -439,10 +506,13 @@ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; reg = <0x7000d400 0x200>; interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 15>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA30_CLK_SBC1>; + resets = <&tegra_car 41>; + reset-names = "spi"; + dmas = <&apbdma 15>, <&apbdma 15>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -450,10 +520,13 @@ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; reg = <0x7000d600 0x200>; interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 16>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA30_CLK_SBC2>; + resets = <&tegra_car 44>; + reset-names = "spi"; + dmas = <&apbdma 16>, <&apbdma 16>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -461,10 +534,13 @@ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; reg = <0x7000d800 0x200>; interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 17>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA30_CLK_SBC3>; + resets = <&tegra_car 46>; + reset-names = "spi"; + dmas = <&apbdma 17>, <&apbdma 17>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -472,10 +548,13 @@ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; reg = <0x7000da00 0x200>; interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 18>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA30_CLK_SBC4>; + resets = <&tegra_car 68>; + reset-names = "spi"; + dmas = <&apbdma 18>, <&apbdma 18>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -483,10 +562,13 @@ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; reg = <0x7000dc00 0x200>; interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 27>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA30_CLK_SBC5>; + resets = <&tegra_car 104>; + reset-names = "spi"; + dmas = <&apbdma 27>, <&apbdma 27>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -494,10 +576,13 @@ compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; reg = <0x7000de00 0x200>; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 28>; #address-cells = <1>; #size-cells = <0>; clocks = <&tegra_car TEGRA30_CLK_SBC6>; + resets = <&tegra_car 106>; + reset-names = "spi"; + dmas = <&apbdma 28>, <&apbdma 28>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -506,6 +591,8 @@ reg = <0x7000e200 0x100>; interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_KBC>; + resets = <&tegra_car 36>; + reset-names = "kbc"; status = "disabled"; }; @@ -540,21 +627,29 @@ reg = <0x70080000 0x200 0x70080200 0x100>; interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - nvidia,dma-request-selector = <&apbdma 1>; clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, - <&tegra_car TEGRA30_CLK_APBIF>, - <&tegra_car TEGRA30_CLK_I2S0>, - <&tegra_car TEGRA30_CLK_I2S1>, - <&tegra_car TEGRA30_CLK_I2S2>, - <&tegra_car TEGRA30_CLK_I2S3>, - <&tegra_car TEGRA30_CLK_I2S4>, - <&tegra_car TEGRA30_CLK_DAM0>, - <&tegra_car TEGRA30_CLK_DAM1>, - <&tegra_car TEGRA30_CLK_DAM2>, - <&tegra_car TEGRA30_CLK_SPDIF_IN>; - clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", + <&tegra_car TEGRA30_CLK_APBIF>; + clock-names = "d_audio", "apbif"; + resets = <&tegra_car 106>, /* d_audio */ + <&tegra_car 107>, /* apbif */ + <&tegra_car 30>, /* i2s0 */ + <&tegra_car 11>, /* i2s1 */ + <&tegra_car 18>, /* i2s2 */ + <&tegra_car 101>, /* i2s3 */ + <&tegra_car 102>, /* i2s4 */ + <&tegra_car 108>, /* dam0 */ + <&tegra_car 109>, /* dam1 */ + <&tegra_car 110>, /* dam2 */ + <&tegra_car 10>; /* spdif */ + reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", "i2s3", "i2s4", "dam0", "dam1", "dam2", - "spdif_in"; + "spdif"; + dmas = <&apbdma 1>, <&apbdma 1>, + <&apbdma 2>, <&apbdma 2>, + <&apbdma 3>, <&apbdma 3>, + <&apbdma 4>, <&apbdma 4>; + dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", + "rx3", "tx3"; ranges; #address-cells = <1>; #size-cells = <1>; @@ -564,6 +659,8 @@ reg = <0x70080300 0x100>; nvidia,ahub-cif-ids = <4 4>; clocks = <&tegra_car TEGRA30_CLK_I2S0>; + resets = <&tegra_car 30>; + reset-names = "i2s"; status = "disabled"; }; @@ -572,6 +669,8 @@ reg = <0x70080400 0x100>; nvidia,ahub-cif-ids = <5 5>; clocks = <&tegra_car TEGRA30_CLK_I2S1>; + resets = <&tegra_car 11>; + reset-names = "i2s"; status = "disabled"; }; @@ -580,6 +679,8 @@ reg = <0x70080500 0x100>; nvidia,ahub-cif-ids = <6 6>; clocks = <&tegra_car TEGRA30_CLK_I2S2>; + resets = <&tegra_car 18>; + reset-names = "i2s"; status = "disabled"; }; @@ -588,6 +689,8 @@ reg = <0x70080600 0x100>; nvidia,ahub-cif-ids = <7 7>; clocks = <&tegra_car TEGRA30_CLK_I2S3>; + resets = <&tegra_car 101>; + reset-names = "i2s"; status = "disabled"; }; @@ -596,6 +699,8 @@ reg = <0x70080700 0x100>; nvidia,ahub-cif-ids = <8 8>; clocks = <&tegra_car TEGRA30_CLK_I2S4>; + resets = <&tegra_car 102>; + reset-names = "i2s"; status = "disabled"; }; }; @@ -605,6 +710,8 @@ reg = <0x78000000 0x200>; interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; + resets = <&tegra_car 14>; + reset-names = "sdhci"; status = "disabled"; }; @@ -613,6 +720,8 @@ reg = <0x78000200 0x200>; interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; + resets = <&tegra_car 9>; + reset-names = "sdhci"; status = "disabled"; }; @@ -621,6 +730,8 @@ reg = <0x78000400 0x200>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; + resets = <&tegra_car 69>; + reset-names = "sdhci"; status = "disabled"; }; @@ -629,6 +740,8 @@ reg = <0x78000600 0x200>; interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; + resets = <&tegra_car 15>; + reset-names = "sdhci"; status = "disabled"; }; @@ -638,6 +751,8 @@ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; phy_type = "utmi"; clocks = <&tegra_car TEGRA30_CLK_USBD>; + resets = <&tegra_car 22>; + reset-names = "usb"; nvidia,needs-double-reset; nvidia,phy = <&phy1>; status = "disabled"; @@ -671,6 +786,8 @@ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; phy_type = "ulpi"; clocks = <&tegra_car TEGRA30_CLK_USB2>; + resets = <&tegra_car 58>; + reset-names = "usb"; nvidia,phy = <&phy2>; status = "disabled"; }; @@ -692,6 +809,8 @@ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; phy_type = "utmi"; clocks = <&tegra_car TEGRA30_CLK_USB3>; + resets = <&tegra_car 59>; + reset-names = "usb"; nvidia,phy = <&phy3>; status = "disabled"; }; diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index 690e89273230..0b4e9b5210d8 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -22,7 +22,6 @@ CONFIG_SOC_AT91SAM9X5=y CONFIG_SOC_AT91SAM9N12=y CONFIG_MACH_AT91RM9200_DT=y CONFIG_MACH_AT91SAM9_DT=y -CONFIG_AT91_PROGRAMMABLE_CLOCKS=y CONFIG_AT91_TIMER_HZ=128 CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set diff --git a/arch/arm/configs/at91rm9200_defconfig b/arch/arm/configs/at91rm9200_defconfig index 75502c4d222c..bf057719dab0 100644 --- a/arch/arm/configs/at91rm9200_defconfig +++ b/arch/arm/configs/at91rm9200_defconfig @@ -31,7 +31,6 @@ CONFIG_MACH_YL9200=y CONFIG_MACH_CPUAT91=y CONFIG_MACH_ECO920=y CONFIG_MTD_AT91_DATAFLASH_CARD=y -CONFIG_AT91_PROGRAMMABLE_CLOCKS=y CONFIG_AT91_TIMER_HZ=100 # CONFIG_ARM_THUMB is not set CONFIG_PCCARD=y diff --git a/arch/arm/configs/at91sam9260_9g20_defconfig b/arch/arm/configs/at91sam9260_9g20_defconfig index 69b6928d3d9d..2cd832918e9c 100644 --- a/arch/arm/configs/at91sam9260_9g20_defconfig +++ b/arch/arm/configs/at91sam9260_9g20_defconfig @@ -15,7 +15,6 @@ CONFIG_MACH_AT91SAM9260EK=y CONFIG_MACH_CAM60=y CONFIG_MACH_SAM9_L9260=y CONFIG_MACH_AFEB9260=y -CONFIG_MACH_QIL_A9260=y CONFIG_MACH_CPU9260=y CONFIG_MACH_FLEXIBITY=y CONFIG_MACH_AT91SAM9G20EK=y @@ -28,7 +27,6 @@ CONFIG_MACH_PCONTROL_G20=y CONFIG_MACH_GSIA18S=y CONFIG_MACH_SNAPPER_9260=y CONFIG_MACH_AT91SAM9_DT=y -CONFIG_AT91_PROGRAMMABLE_CLOCKS=y CONFIG_AT91_SLOW_CLOCK=y # CONFIG_ARM_THUMB is not set CONFIG_AEABI=y diff --git a/arch/arm/configs/at91sam9261_9g10_defconfig b/arch/arm/configs/at91sam9261_9g10_defconfig index 9d35cd81c611..f80e993b04ce 100644 --- a/arch/arm/configs/at91sam9261_9g10_defconfig +++ b/arch/arm/configs/at91sam9261_9g10_defconfig @@ -18,7 +18,6 @@ CONFIG_ARCH_AT91=y CONFIG_ARCH_AT91SAM9261=y CONFIG_MACH_AT91SAM9261EK=y CONFIG_MACH_AT91SAM9G10EK=y -CONFIG_AT91_PROGRAMMABLE_CLOCKS=y # CONFIG_ARM_THUMB is not set CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set diff --git a/arch/arm/configs/at91sam9g45_defconfig b/arch/arm/configs/at91sam9g45_defconfig index 08166cd4e7d6..e181a50fd65a 100644 --- a/arch/arm/configs/at91sam9g45_defconfig +++ b/arch/arm/configs/at91sam9g45_defconfig @@ -18,7 +18,6 @@ CONFIG_ARCH_AT91=y CONFIG_ARCH_AT91SAM9G45=y CONFIG_MACH_AT91SAM9M10G45EK=y CONFIG_MACH_AT91SAM9_DT=y -CONFIG_AT91_PROGRAMMABLE_CLOCKS=y CONFIG_AT91_SLOW_CLOCK=y CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set diff --git a/arch/arm/configs/at91sam9rl_defconfig b/arch/arm/configs/at91sam9rl_defconfig index 7cf87856d63c..7b6f131cecd6 100644 --- a/arch/arm/configs/at91sam9rl_defconfig +++ b/arch/arm/configs/at91sam9rl_defconfig @@ -13,7 +13,6 @@ CONFIG_MODULE_UNLOAD=y CONFIG_ARCH_AT91=y CONFIG_ARCH_AT91SAM9RL=y CONFIG_MACH_AT91SAM9RLEK=y -CONFIG_AT91_PROGRAMMABLE_CLOCKS=y # CONFIG_ARM_THUMB is not set CONFIG_ZBOOT_ROM_TEXT=0x0 CONFIG_ZBOOT_ROM_BSS=0x0 diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig index f6e78f83c3c3..dc3881e07630 100644 --- a/arch/arm/configs/sama5_defconfig +++ b/arch/arm/configs/sama5_defconfig @@ -20,7 +20,6 @@ CONFIG_ARCH_AT91=y CONFIG_SOC_SAM_V7=y CONFIG_SOC_SAMA5D3=y CONFIG_MACH_SAMA5_DT=y -CONFIG_AT91_PROGRAMMABLE_CLOCKS=y CONFIG_AEABI=y # CONFIG_OABI_COMPAT is not set CONFIG_UACCESS_WITH_MEMCPY=y diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 699b71e7f7ec..f1bf952da747 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -1,15 +1,33 @@ if ARCH_AT91 +config HAVE_AT91_UTMI + bool + +config HAVE_AT91_USB_CLK + bool + config HAVE_AT91_DBGU0 bool config HAVE_AT91_DBGU1 bool +config AT91_USE_OLD_CLK + bool + config AT91_PMC_UNIT bool default !ARCH_AT91X40 +config COMMON_CLK_AT91 + bool + default AT91_PMC_UNIT && USE_OF && !AT91_USE_OLD_CLK + select COMMON_CLK + +config OLD_CLK_AT91 + bool + default AT91_PMC_UNIT && AT91_USE_OLD_CLK + config AT91_SAM9_ALT_RESET bool default !ARCH_AT91X40 @@ -21,6 +39,9 @@ config AT91_SAM9G45_RESET config AT91_SAM9_TIME bool +config HAVE_AT91_SMD + bool + config SOC_AT91SAM9 bool select AT91_SAM9_TIME @@ -61,10 +82,12 @@ comment "Atmel AT91 Processor" if SOC_SAM_V7 config SOC_SAMA5D3 bool "SAMA5D3 family" - depends on SOC_SAM_V7 select SOC_SAMA5 select HAVE_FB_ATMEL select HAVE_AT91_DBGU1 + select HAVE_AT91_UTMI + select HAVE_AT91_SMD + select HAVE_AT91_USB_CLK help Select this if you are using one of Atmel's SAMA5D3 family SoC. This support covers SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35. @@ -78,11 +101,15 @@ config SOC_AT91RM9200 select HAVE_AT91_DBGU0 select MULTI_IRQ_HANDLER select SPARSE_IRQ + select AT91_USE_OLD_CLK + select HAVE_AT91_USB_CLK config SOC_AT91SAM9260 bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20" select HAVE_AT91_DBGU0 select SOC_AT91SAM9 + select AT91_USE_OLD_CLK + select HAVE_AT91_USB_CLK help Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE or AT91SAM9G20 SoC. @@ -92,6 +119,8 @@ config SOC_AT91SAM9261 select HAVE_AT91_DBGU0 select HAVE_FB_ATMEL select SOC_AT91SAM9 + select AT91_USE_OLD_CLK + select HAVE_AT91_USB_CLK help Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC. @@ -100,18 +129,25 @@ config SOC_AT91SAM9263 select HAVE_AT91_DBGU1 select HAVE_FB_ATMEL select SOC_AT91SAM9 + select AT91_USE_OLD_CLK + select HAVE_AT91_USB_CLK config SOC_AT91SAM9RL bool "AT91SAM9RL" select HAVE_AT91_DBGU0 select HAVE_FB_ATMEL select SOC_AT91SAM9 + select AT91_USE_OLD_CLK + select HAVE_AT91_UTMI config SOC_AT91SAM9G45 bool "AT91SAM9G45 or AT91SAM9M10 families" select HAVE_AT91_DBGU1 select HAVE_FB_ATMEL select SOC_AT91SAM9 + select AT91_USE_OLD_CLK + select HAVE_AT91_UTMI + select HAVE_AT91_USB_CLK help Select this if you are using one of Atmel's AT91SAM9G45 family SoC. This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11. @@ -121,6 +157,10 @@ config SOC_AT91SAM9X5 select HAVE_AT91_DBGU0 select HAVE_FB_ATMEL select SOC_AT91SAM9 + select AT91_USE_OLD_CLK + select HAVE_AT91_UTMI + select HAVE_AT91_SMD + select HAVE_AT91_USB_CLK help Select this if you are using one of Atmel's AT91SAM9x5 family SoC. This means that your SAM9 name finishes with a '5' (except if it is @@ -133,6 +173,8 @@ config SOC_AT91SAM9N12 select HAVE_AT91_DBGU0 select HAVE_FB_ATMEL select SOC_AT91SAM9 + select AT91_USE_OLD_CLK + select HAVE_AT91_USB_CLK help Select this if you are using Atmel's AT91SAM9N12 SoC. @@ -172,12 +214,6 @@ config MACH_SAMA5_DT comment "AT91 Feature Selections" -config AT91_PROGRAMMABLE_CLOCKS - bool "Programmable Clocks" - help - Select this if you need to program one or more of the PCK0..PCK3 - programmable clock outputs. - config AT91_SLOW_CLOCK bool "Suspend-to-RAM disables main oscillator" depends on SUSPEND diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt index 0363dba7d3f6..1f73e9b527da 100644 --- a/arch/arm/mach-at91/Kconfig.non_dt +++ b/arch/arm/mach-at91/Kconfig.non_dt @@ -12,26 +12,32 @@ config ARCH_AT91_NONE config ARCH_AT91RM9200 bool "AT91RM9200" select SOC_AT91RM9200 + select AT91_USE_OLD_CLK config ARCH_AT91SAM9260 bool "AT91SAM9260 or AT91SAM9XE or AT91SAM9G20" select SOC_AT91SAM9260 + select AT91_USE_OLD_CLK config ARCH_AT91SAM9261 bool "AT91SAM9261 or AT91SAM9G10" select SOC_AT91SAM9261 + select AT91_USE_OLD_CLK config ARCH_AT91SAM9263 bool "AT91SAM9263" select SOC_AT91SAM9263 + select AT91_USE_OLD_CLK config ARCH_AT91SAM9RL bool "AT91SAM9RL" select SOC_AT91SAM9RL + select AT91_USE_OLD_CLK config ARCH_AT91SAM9G45 bool "AT91SAM9G45" select SOC_AT91SAM9G45 + select AT91_USE_OLD_CLK config ARCH_AT91X40 bool "AT91x40" @@ -176,12 +182,6 @@ config MACH_AFEB9260 <svn://194.85.238.22/home/users/george/svn/arm9eb> <http://groups.google.com/group/arm9fpga-evolution-board> -config MACH_QIL_A9260 - bool "CALAO QIL-A9260 board" - help - Select this if you are using a Calao Systems QIL-A9260 Board. - <http://www.calao-systems.com> - config MACH_CPU9260 bool "Eukrea CPU9260 board" help diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 90aab2d5a07f..78e9cec282f4 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -7,7 +7,7 @@ obj-m := obj-n := obj- := -obj-$(CONFIG_AT91_PMC_UNIT) += clock.o +obj-$(CONFIG_OLD_CLK_AT91) += clock.o obj-$(CONFIG_AT91_SAM9_ALT_RESET) += at91sam9_alt_reset.o obj-$(CONFIG_AT91_SAM9G45_RESET) += at91sam9g45_reset.o obj-$(CONFIG_AT91_SAM9_TIME) += at91sam926x_time.o @@ -52,7 +52,6 @@ obj-$(CONFIG_MACH_RSI_EWS) += board-rsi-ews.o obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o obj-$(CONFIG_MACH_CAM60) += board-cam60.o obj-$(CONFIG_MACH_SAM9_L9260) += board-sam9-l9260.o -obj-$(CONFIG_MACH_QIL_A9260) += board-qil-a9260.o obj-$(CONFIG_MACH_AFEB9260) += board-afeb-9260v1.o obj-$(CONFIG_MACH_CPU9260) += board-cpu9krea.o obj-$(CONFIG_MACH_FLEXIBITY) += board-flexibity.o diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c index 25805f2f6010..e47f5fd232f5 100644 --- a/arch/arm/mach-at91/at91rm9200.c +++ b/arch/arm/mach-at91/at91rm9200.c @@ -12,13 +12,13 @@ #include <linux/module.h> #include <linux/reboot.h> +#include <linux/clk/at91_pmc.h> #include <asm/irq.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/system_misc.h> #include <mach/at91rm9200.h> -#include <mach/at91_pmc.h> #include <mach/at91_st.h> #include <mach/cpu.h> diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c index d6a1fa85371d..6c821e562159 100644 --- a/arch/arm/mach-at91/at91sam9260.c +++ b/arch/arm/mach-at91/at91sam9260.c @@ -11,6 +11,7 @@ */ #include <linux/module.h> +#include <linux/clk/at91_pmc.h> #include <asm/proc-fns.h> #include <asm/irq.h> @@ -20,7 +21,6 @@ #include <mach/cpu.h> #include <mach/at91_dbgu.h> #include <mach/at91sam9260.h> -#include <mach/at91_pmc.h> #include "at91_aic.h" #include "at91_rstc.h" diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c index 23ba1d8a1531..6276b4c1acfe 100644 --- a/arch/arm/mach-at91/at91sam9261.c +++ b/arch/arm/mach-at91/at91sam9261.c @@ -11,6 +11,7 @@ */ #include <linux/module.h> +#include <linux/clk/at91_pmc.h> #include <asm/proc-fns.h> #include <asm/irq.h> @@ -19,7 +20,6 @@ #include <asm/system_misc.h> #include <mach/cpu.h> #include <mach/at91sam9261.h> -#include <mach/at91_pmc.h> #include "at91_aic.h" #include "at91_rstc.h" diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c index 7eccb0fc57bc..37b90f4b990c 100644 --- a/arch/arm/mach-at91/at91sam9263.c +++ b/arch/arm/mach-at91/at91sam9263.c @@ -11,6 +11,7 @@ */ #include <linux/module.h> +#include <linux/clk/at91_pmc.h> #include <asm/proc-fns.h> #include <asm/irq.h> @@ -18,7 +19,6 @@ #include <asm/mach/map.h> #include <asm/system_misc.h> #include <mach/at91sam9263.h> -#include <mach/at91_pmc.h> #include "at91_aic.h" #include "at91_rstc.h" diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c index bb392320a0dd..0f04ffe9c5a8 100644 --- a/arch/arm/mach-at91/at91sam926x_time.c +++ b/arch/arm/mach-at91/at91sam926x_time.c @@ -39,6 +39,7 @@ static u32 pit_cycle; /* write-once */ static u32 pit_cnt; /* access only w/system irq blocked */ static void __iomem *pit_base_addr __read_mostly; +static struct clk *mck; static inline unsigned int pit_read(unsigned int reg_offset) { @@ -195,10 +196,14 @@ static int __init of_at91sam926x_pit_init(void) if (!pit_base_addr) goto node_err; + mck = of_clk_get(np, 0); + /* Get the interrupts property */ ret = irq_of_parse_and_map(np, 0); if (!ret) { pr_crit("AT91: PIT: Unable to get IRQ from DT\n"); + if (!IS_ERR(mck)) + clk_put(mck); goto ioremap_err; } at91sam926x_pit_irq.irq = ret; @@ -230,6 +235,8 @@ void __init at91sam926x_pit_init(void) unsigned bits; int ret; + mck = ERR_PTR(-ENOENT); + /* For device tree enabled device: initialize here */ of_at91sam926x_pit_init(); @@ -237,7 +244,12 @@ void __init at91sam926x_pit_init(void) * Use our actual MCK to figure out how many MCK/16 ticks per * 1/HZ period (instead of a compile-time constant LATCH). */ - pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16; + if (IS_ERR(mck)) + mck = clk_get(NULL, "mck"); + + if (IS_ERR(mck)) + panic("AT91: PIT: Unable to get mck clk\n"); + pit_rate = clk_get_rate(mck) / 16; pit_cycle = (pit_rate + HZ/2) / HZ; WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0); diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c index 9405aa08b104..2f455ce35268 100644 --- a/arch/arm/mach-at91/at91sam9g45.c +++ b/arch/arm/mach-at91/at91sam9g45.c @@ -12,13 +12,13 @@ #include <linux/module.h> #include <linux/dma-mapping.h> +#include <linux/clk/at91_pmc.h> #include <asm/irq.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/system_misc.h> #include <mach/at91sam9g45.h> -#include <mach/at91_pmc.h> #include <mach/cpu.h> #include "at91_aic.h" diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c index 388ec3aec4b9..4ef088c62eab 100644 --- a/arch/arm/mach-at91/at91sam9n12.c +++ b/arch/arm/mach-at91/at91sam9n12.c @@ -8,12 +8,12 @@ #include <linux/module.h> #include <linux/dma-mapping.h> +#include <linux/clk/at91_pmc.h> #include <asm/irq.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <mach/at91sam9n12.h> -#include <mach/at91_pmc.h> #include <mach/cpu.h> #include "board.h" diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c index 0750ffb7e6b1..3651517abedf 100644 --- a/arch/arm/mach-at91/at91sam9rl.c +++ b/arch/arm/mach-at91/at91sam9rl.c @@ -10,6 +10,7 @@ */ #include <linux/module.h> +#include <linux/clk/at91_pmc.h> #include <asm/proc-fns.h> #include <asm/irq.h> @@ -19,7 +20,6 @@ #include <mach/cpu.h> #include <mach/at91_dbgu.h> #include <mach/at91sam9rl.h> -#include <mach/at91_pmc.h> #include "at91_aic.h" #include "at91_rstc.h" diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c index e8a2e075a1b8..3e8ec26e39dc 100644 --- a/arch/arm/mach-at91/at91sam9x5.c +++ b/arch/arm/mach-at91/at91sam9x5.c @@ -8,12 +8,12 @@ #include <linux/module.h> #include <linux/dma-mapping.h> +#include <linux/clk/at91_pmc.h> #include <asm/irq.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <mach/at91sam9x5.h> -#include <mach/at91_pmc.h> #include <mach/cpu.h> #include "board.h" diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c index bf00d15d954d..075ec0576ada 100644 --- a/arch/arm/mach-at91/board-dt-sama5.c +++ b/arch/arm/mach-at91/board-dt-sama5.c @@ -16,6 +16,7 @@ #include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/phy.h> +#include <linux/clk-provider.h> #include <asm/setup.h> #include <asm/irq.h> @@ -26,6 +27,13 @@ #include "at91_aic.h" #include "generic.h" +static void __init sama5_dt_timer_init(void) +{ +#if defined(CONFIG_COMMON_CLK) + of_clk_init(NULL); +#endif + at91sam926x_pit_init(); +} static const struct of_device_id irq_of_match[] __initconst = { @@ -72,7 +80,7 @@ static const char *sama5_dt_board_compat[] __initdata = { DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)") /* Maintainer: Atmel */ - .init_time = at91sam926x_pit_init, + .init_time = sama5_dt_timer_init, .map_io = at91_map_io, .handle_irq = at91_aic5_handle_irq, .init_early = at91_dt_initialize, diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c deleted file mode 100644 index aa3bc9b0f150..000000000000 --- a/arch/arm/mach-at91/board-qil-a9260.c +++ /dev/null @@ -1,266 +0,0 @@ -/* - * linux/arch/arm/mach-at91/board-qil-a9260.c - * - * Copyright (C) 2005 SAN People - * Copyright (C) 2006 Atmel - * Copyright (C) 2007 Calao-systems - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - */ - -#include <linux/types.h> -#include <linux/gpio.h> -#include <linux/init.h> -#include <linux/mm.h> -#include <linux/module.h> -#include <linux/platform_device.h> -#include <linux/spi/spi.h> -#include <linux/gpio_keys.h> -#include <linux/input.h> -#include <linux/clk.h> - -#include <asm/setup.h> -#include <asm/mach-types.h> -#include <asm/irq.h> - -#include <asm/mach/arch.h> -#include <asm/mach/map.h> -#include <asm/mach/irq.h> - -#include <mach/hardware.h> -#include <mach/at91sam9_smc.h> - -#include "at91_aic.h" -#include "at91_shdwc.h" -#include "board.h" -#include "sam9_smc.h" -#include "generic.h" - - -static void __init ek_init_early(void) -{ - /* Initialize processor: 12.000 MHz crystal */ - at91_initialize(12000000); -} - -/* - * USB Host port - */ -static struct at91_usbh_data __initdata ek_usbh_data = { - .ports = 2, - .vbus_pin = {-EINVAL, -EINVAL}, - .overcurrent_pin= {-EINVAL, -EINVAL}, -}; - -/* - * USB Device port - */ -static struct at91_udc_data __initdata ek_udc_data = { - .vbus_pin = AT91_PIN_PC5, - .pullup_pin = -EINVAL, /* pull-up driven by UDC */ -}; - -/* - * SPI devices. - */ -static struct spi_board_info ek_spi_devices[] = { -#if defined(CONFIG_RTC_DRV_M41T94) - { /* M41T94 RTC */ - .modalias = "m41t94", - .chip_select = 0, - .max_speed_hz = 1 * 1000 * 1000, - .bus_num = 0, - } -#endif -}; - -/* - * MACB Ethernet device - */ -static struct macb_platform_data __initdata ek_macb_data = { - .phy_irq_pin = AT91_PIN_PA31, - .is_rmii = 1, -}; - -/* - * NAND flash - */ -static struct mtd_partition __initdata ek_nand_partition[] = { - { - .name = "Uboot & Kernel", - .offset = 0, - .size = SZ_16M, - }, - { - .name = "Root FS", - .offset = MTDPART_OFS_NXTBLK, - .size = 120 * SZ_1M, - }, - { - .name = "FS", - .offset = MTDPART_OFS_NXTBLK, - .size = 120 * SZ_1M, - }, -}; - -static struct atmel_nand_data __initdata ek_nand_data = { - .ale = 21, - .cle = 22, - .det_pin = -EINVAL, - .rdy_pin = AT91_PIN_PC13, - .enable_pin = AT91_PIN_PC14, - .ecc_mode = NAND_ECC_SOFT, - .on_flash_bbt = 1, - .parts = ek_nand_partition, - .num_parts = ARRAY_SIZE(ek_nand_partition), -}; - -static struct sam9_smc_config __initdata ek_nand_smc_config = { - .ncs_read_setup = 0, - .nrd_setup = 1, - .ncs_write_setup = 0, - .nwe_setup = 1, - - .ncs_read_pulse = 3, - .nrd_pulse = 3, - .ncs_write_pulse = 3, - .nwe_pulse = 3, - - .read_cycle = 5, - .write_cycle = 5, - - .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8, - .tdf_cycles = 2, -}; - -static void __init ek_add_device_nand(void) -{ - /* configure chip-select 3 (NAND) */ - sam9_smc_configure(0, 3, &ek_nand_smc_config); - - at91_add_device_nand(&ek_nand_data); -} - -/* - * MCI (SD/MMC) - */ -static struct mci_platform_data __initdata ek_mci0_data = { - .slot[0] = { - .bus_width = 4, - .detect_pin = -EINVAL, - .wp_pin = -EINVAL, - }, -}; - -/* - * GPIO Buttons - */ -#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) -static struct gpio_keys_button ek_buttons[] = { - { /* USER PUSH BUTTON */ - .code = KEY_ENTER, - .gpio = AT91_PIN_PB10, - .active_low = 1, - .desc = "user_pb", - .wakeup = 1, - } -}; - -static struct gpio_keys_platform_data ek_button_data = { - .buttons = ek_buttons, - .nbuttons = ARRAY_SIZE(ek_buttons), -}; - -static struct platform_device ek_button_device = { - .name = "gpio-keys", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &ek_button_data, - } -}; - -static void __init ek_add_device_buttons(void) -{ - at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* user push button, pull up enabled */ - at91_set_deglitch(AT91_PIN_PB10, 1); - - platform_device_register(&ek_button_device); -} -#else -static void __init ek_add_device_buttons(void) {} -#endif - -/* - * LEDs - */ -static struct gpio_led ek_leds[] = { - { /* user_led (green) */ - .name = "user_led", - .gpio = AT91_PIN_PB21, - .active_low = 0, - .default_trigger = "heartbeat", - } -}; - -static void __init ek_board_init(void) -{ - /* Serial */ - /* DBGU on ttyS0. (Rx & Tx only) */ - at91_register_uart(0, 0, 0); - - /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ - at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS - | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD - | ATMEL_UART_RI); - - /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */ - at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); - - /* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */ - at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS); - at91_add_device_serial(); - /* USB Host */ - at91_add_device_usbh(&ek_usbh_data); - /* USB Device */ - at91_add_device_udc(&ek_udc_data); - /* SPI */ - at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); - /* NAND */ - ek_add_device_nand(); - /* I2C */ - at91_add_device_i2c(NULL, 0); - /* Ethernet */ - at91_add_device_eth(&ek_macb_data); - /* MMC */ - at91_add_device_mci(0, &ek_mci0_data); - /* Push Buttons */ - ek_add_device_buttons(); - /* LEDs */ - at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds)); - /* shutdown controller, wakeup button (5 msec low) */ - at91_shdwc_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW - | AT91_SHDW_RTTWKEN); -} - -MACHINE_START(QIL_A9260, "CALAO QIL_A9260") - /* Maintainer: calao-systems */ - .init_time = at91sam926x_pit_init, - .map_io = at91_map_io, - .handle_irq = at91_aic_handle_irq, - .init_early = ek_init_early, - .init_irq = at91_init_irq_default, - .init_machine = ek_board_init, -MACHINE_END diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c index 6b2630a92f71..034529d801b2 100644 --- a/arch/arm/mach-at91/clock.c +++ b/arch/arm/mach-at91/clock.c @@ -24,9 +24,9 @@ #include <linux/clk.h> #include <linux/io.h> #include <linux/of_address.h> +#include <linux/clk/at91_pmc.h> #include <mach/hardware.h> -#include <mach/at91_pmc.h> #include <mach/cpu.h> #include <asm/proc-fns.h> @@ -330,8 +330,6 @@ EXPORT_SYMBOL(clk_get_rate); /*------------------------------------------------------------------------*/ -#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS - /* * For now, only the programmable clocks support reparenting (MCK could * do this too, with care) or rate changing (the PLLs could do this too, @@ -459,8 +457,6 @@ static void __init init_programmable_clock(struct clk *clk) clk->rate_hz = parent->rate_hz / pmc_prescaler_divider(pckr); } -#endif /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */ - /*------------------------------------------------------------------------*/ #ifdef CONFIG_DEBUG_FS @@ -577,12 +573,10 @@ int __init clk_register(struct clk *clk) clk->parent = &mck; clk->mode = pmc_sys_mode; } -#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS else if (clk_is_programmable(clk)) { clk->mode = pmc_sys_mode; init_programmable_clock(clk); } -#endif at91_clk_add(clk); @@ -884,6 +878,11 @@ static int __init at91_pmc_init(unsigned long main_clock) #if defined(CONFIG_OF) static struct of_device_id pmc_ids[] = { { .compatible = "atmel,at91rm9200-pmc" }, + { .compatible = "atmel,at91sam9260-pmc" }, + { .compatible = "atmel,at91sam9g45-pmc" }, + { .compatible = "atmel,at91sam9n12-pmc" }, + { .compatible = "atmel,at91sam9x5-pmc" }, + { .compatible = "atmel,sama5d3-pmc" }, { /*sentinel*/ } }; diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h index 26dee3ce9397..631fa3b8c16d 100644 --- a/arch/arm/mach-at91/generic.h +++ b/arch/arm/mach-at91/generic.h @@ -46,11 +46,12 @@ extern void at91sam926x_pit_init(void); extern void at91x40_timer_init(void); /* Clocks */ -#ifdef CONFIG_AT91_PMC_UNIT +#ifdef CONFIG_OLD_CLK_AT91 extern int __init at91_clock_init(unsigned long main_clock); extern int __init at91_dt_clock_init(void); #else static int inline at91_clock_init(unsigned long main_clock) { return 0; } +static int inline at91_dt_clock_init(void) { return 0; } #endif struct device; diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h deleted file mode 100644 index c604cc69acb5..000000000000 --- a/arch/arm/mach-at91/include/mach/at91_pmc.h +++ /dev/null @@ -1,190 +0,0 @@ -/* - * arch/arm/mach-at91/include/mach/at91_pmc.h - * - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) SAN People - * - * Power Management Controller (PMC) - System peripherals registers. - * Based on AT91RM9200 datasheet revision E. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#ifndef AT91_PMC_H -#define AT91_PMC_H - -#ifndef __ASSEMBLY__ -extern void __iomem *at91_pmc_base; - -#define at91_pmc_read(field) \ - __raw_readl(at91_pmc_base + field) - -#define at91_pmc_write(field, value) \ - __raw_writel(value, at91_pmc_base + field) -#else -.extern at91_pmc_base -#endif - -#define AT91_PMC_SCER 0x00 /* System Clock Enable Register */ -#define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */ - -#define AT91_PMC_SCSR 0x08 /* System Clock Status Register */ -#define AT91_PMC_PCK (1 << 0) /* Processor Clock */ -#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ -#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ -#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ -#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ -#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ -#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ -#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ -#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ -#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ -#define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */ -#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ -#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ - -#define AT91_PMC_PCER 0x10 /* Peripheral Clock Enable Register */ -#define AT91_PMC_PCDR 0x14 /* Peripheral Clock Disable Register */ -#define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */ - -#define AT91_CKGR_UCKR 0x1C /* UTMI Clock Register [some SAM9] */ -#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ -#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ -#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ -#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */ - -#define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */ -#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ -#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */ -#define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */ -#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ -#define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */ -#define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */ -#define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */ - -#define AT91_CKGR_MCFR 0x24 /* Main Clock Frequency Register */ -#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ -#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ - -#define AT91_CKGR_PLLAR 0x28 /* PLL A Register */ -#define AT91_CKGR_PLLBR 0x2c /* PLL B Register */ -#define AT91_PMC_DIV (0xff << 0) /* Divider */ -#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ -#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ -#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ -#define AT91_PMC_MUL_GET(n) ((n) >> 16 & 0x7ff) -#define AT91_PMC3_MUL (0x7f << 18) /* PLL Multiplier [SAMA5 only] */ -#define AT91_PMC3_MUL_GET(n) ((n) >> 18 & 0x7f) -#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ -#define AT91_PMC_USBDIV_1 (0 << 28) -#define AT91_PMC_USBDIV_2 (1 << 28) -#define AT91_PMC_USBDIV_4 (2 << 28) -#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ - -#define AT91_PMC_MCKR 0x30 /* Master Clock Register */ -#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ -#define AT91_PMC_CSS_SLOW (0 << 0) -#define AT91_PMC_CSS_MAIN (1 << 0) -#define AT91_PMC_CSS_PLLA (2 << 0) -#define AT91_PMC_CSS_PLLB (3 << 0) -#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */ -#define PMC_PRES_OFFSET 2 -#define AT91_PMC_PRES (7 << PMC_PRES_OFFSET) /* Master Clock Prescaler */ -#define AT91_PMC_PRES_1 (0 << PMC_PRES_OFFSET) -#define AT91_PMC_PRES_2 (1 << PMC_PRES_OFFSET) -#define AT91_PMC_PRES_4 (2 << PMC_PRES_OFFSET) -#define AT91_PMC_PRES_8 (3 << PMC_PRES_OFFSET) -#define AT91_PMC_PRES_16 (4 << PMC_PRES_OFFSET) -#define AT91_PMC_PRES_32 (5 << PMC_PRES_OFFSET) -#define AT91_PMC_PRES_64 (6 << PMC_PRES_OFFSET) -#define PMC_ALT_PRES_OFFSET 4 -#define AT91_PMC_ALT_PRES (7 << PMC_ALT_PRES_OFFSET) /* Master Clock Prescaler [alternate location] */ -#define AT91_PMC_ALT_PRES_1 (0 << PMC_ALT_PRES_OFFSET) -#define AT91_PMC_ALT_PRES_2 (1 << PMC_ALT_PRES_OFFSET) -#define AT91_PMC_ALT_PRES_4 (2 << PMC_ALT_PRES_OFFSET) -#define AT91_PMC_ALT_PRES_8 (3 << PMC_ALT_PRES_OFFSET) -#define AT91_PMC_ALT_PRES_16 (4 << PMC_ALT_PRES_OFFSET) -#define AT91_PMC_ALT_PRES_32 (5 << PMC_ALT_PRES_OFFSET) -#define AT91_PMC_ALT_PRES_64 (6 << PMC_ALT_PRES_OFFSET) -#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ -#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ -#define AT91RM9200_PMC_MDIV_2 (1 << 8) -#define AT91RM9200_PMC_MDIV_3 (2 << 8) -#define AT91RM9200_PMC_MDIV_4 (3 << 8) -#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */ -#define AT91SAM9_PMC_MDIV_2 (1 << 8) -#define AT91SAM9_PMC_MDIV_4 (2 << 8) -#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */ -#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ -#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ -#define AT91_PMC_PDIV_1 (0 << 12) -#define AT91_PMC_PDIV_2 (1 << 12) -#define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */ -#define AT91_PMC_PLLADIV2_OFF (0 << 12) -#define AT91_PMC_PLLADIV2_ON (1 << 12) - -#define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */ -#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */ -#define AT91_PMC_USBS_PLLA (0 << 0) -#define AT91_PMC_USBS_UPLL (1 << 0) -#define AT91_PMC_USBS_PLLB (1 << 0) /* [AT91SAMN12 only] */ -#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */ -#define AT91_PMC_OHCIUSBDIV_1 (0x0 << 8) -#define AT91_PMC_OHCIUSBDIV_2 (0x1 << 8) - -#define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */ -#define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */ -#define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */ -#define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV) - -#define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ -#define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */ -#define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */ -#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */ -#define AT91_PMC_CSSMCK_CSS (0 << 8) -#define AT91_PMC_CSSMCK_MCK (1 << 8) - -#define AT91_PMC_IER 0x60 /* Interrupt Enable Register */ -#define AT91_PMC_IDR 0x64 /* Interrupt Disable Register */ -#define AT91_PMC_SR 0x68 /* Status Register */ -#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ -#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ -#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ -#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ -#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9] */ -#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ -#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ -#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ -#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ -#define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */ -#define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */ -#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */ -#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */ - -#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */ -#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */ -#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */ -#define AT91_PMC_PROTKEY (0x504d43 << 8) /* Activation Code */ - -#define AT91_PMC_WPSR 0xe8 /* Write Protect Status Register [some SAM9] */ -#define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */ -#define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */ - -#define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/ -#define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Enable Register 1 */ -#define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */ - -#define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9 and SAMA5] */ -#define AT91_PMC_PCR_PID (0x3f << 0) /* Peripheral ID */ -#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */ -#define AT91_PMC_PCR_DIV(n) ((n) << 16) /* Divisor Value */ -#define AT91_PMC_PCR_DIV0 0x0 /* Peripheral clock is MCK */ -#define AT91_PMC_PCR_DIV2 0x1 /* Peripheral clock is MCK/2 */ -#define AT91_PMC_PCR_DIV4 0x2 /* Peripheral clock is MCK/4 */ -#define AT91_PMC_PCR_DIV8 0x3 /* Peripheral clock is MCK/8 */ -#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ - -#endif diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index 9986542e8060..590b52dea9f7 100644 --- a/arch/arm/mach-at91/pm.c +++ b/arch/arm/mach-at91/pm.c @@ -19,13 +19,13 @@ #include <linux/module.h> #include <linux/platform_device.h> #include <linux/io.h> +#include <linux/clk/at91_pmc.h> #include <asm/irq.h> #include <linux/atomic.h> #include <asm/mach/time.h> #include <asm/mach/irq.h> -#include <mach/at91_pmc.h> #include <mach/cpu.h> #include "at91_aic.h" @@ -155,9 +155,6 @@ static int at91_pm_verify_clocks(void) } } - if (!IS_ENABLED(CONFIG_AT91_PROGRAMMABLE_CLOCKS)) - return 1; - /* PCK0..PCK3 must be disabled, or configured to use clk32k */ for (i = 0; i < 4; i++) { u32 css; diff --git a/arch/arm/mach-at91/pm_slowclock.S b/arch/arm/mach-at91/pm_slowclock.S index 098c28ddf025..20018779bae7 100644 --- a/arch/arm/mach-at91/pm_slowclock.S +++ b/arch/arm/mach-at91/pm_slowclock.S @@ -13,8 +13,8 @@ */ #include <linux/linkage.h> +#include <linux/clk/at91_pmc.h> #include <mach/hardware.h> -#include <mach/at91_pmc.h> #include <mach/at91_ramc.h> diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c index a28873fe3049..3d775d08de08 100644 --- a/arch/arm/mach-at91/sama5d3.c +++ b/arch/arm/mach-at91/sama5d3.c @@ -9,360 +9,19 @@ #include <linux/module.h> #include <linux/dma-mapping.h> +#include <linux/clk/at91_pmc.h> #include <asm/irq.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <mach/sama5d3.h> -#include <mach/at91_pmc.h> #include <mach/cpu.h> #include "soc.h" #include "generic.h" -#include "clock.h" #include "sam9_smc.h" /* -------------------------------------------------------------------- - * Clocks - * -------------------------------------------------------------------- */ - -/* - * The peripheral clocks. - */ - -static struct clk pioA_clk = { - .name = "pioA_clk", - .pid = SAMA5D3_ID_PIOA, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk pioB_clk = { - .name = "pioB_clk", - .pid = SAMA5D3_ID_PIOB, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk pioC_clk = { - .name = "pioC_clk", - .pid = SAMA5D3_ID_PIOC, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk pioD_clk = { - .name = "pioD_clk", - .pid = SAMA5D3_ID_PIOD, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk pioE_clk = { - .name = "pioE_clk", - .pid = SAMA5D3_ID_PIOE, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk usart0_clk = { - .name = "usart0_clk", - .pid = SAMA5D3_ID_USART0, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV2, -}; -static struct clk usart1_clk = { - .name = "usart1_clk", - .pid = SAMA5D3_ID_USART1, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV2, -}; -static struct clk usart2_clk = { - .name = "usart2_clk", - .pid = SAMA5D3_ID_USART2, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV2, -}; -static struct clk usart3_clk = { - .name = "usart3_clk", - .pid = SAMA5D3_ID_USART3, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV2, -}; -static struct clk uart0_clk = { - .name = "uart0_clk", - .pid = SAMA5D3_ID_UART0, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV2, -}; -static struct clk uart1_clk = { - .name = "uart1_clk", - .pid = SAMA5D3_ID_UART1, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV2, -}; -static struct clk twi0_clk = { - .name = "twi0_clk", - .pid = SAMA5D3_ID_TWI0, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV8, -}; -static struct clk twi1_clk = { - .name = "twi1_clk", - .pid = SAMA5D3_ID_TWI1, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV8, -}; -static struct clk twi2_clk = { - .name = "twi2_clk", - .pid = SAMA5D3_ID_TWI2, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV8, -}; -static struct clk mmc0_clk = { - .name = "mci0_clk", - .pid = SAMA5D3_ID_HSMCI0, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk mmc1_clk = { - .name = "mci1_clk", - .pid = SAMA5D3_ID_HSMCI1, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk mmc2_clk = { - .name = "mci2_clk", - .pid = SAMA5D3_ID_HSMCI2, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk spi0_clk = { - .name = "spi0_clk", - .pid = SAMA5D3_ID_SPI0, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk spi1_clk = { - .name = "spi1_clk", - .pid = SAMA5D3_ID_SPI1, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk tcb0_clk = { - .name = "tcb0_clk", - .pid = SAMA5D3_ID_TC0, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV2, -}; -static struct clk tcb1_clk = { - .name = "tcb1_clk", - .pid = SAMA5D3_ID_TC1, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV2, -}; -static struct clk adc_clk = { - .name = "adc_clk", - .pid = SAMA5D3_ID_ADC, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV2, -}; -static struct clk adc_op_clk = { - .name = "adc_op_clk", - .type = CLK_TYPE_PERIPHERAL, - .rate_hz = 5000000, -}; -static struct clk dma0_clk = { - .name = "dma0_clk", - .pid = SAMA5D3_ID_DMA0, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk dma1_clk = { - .name = "dma1_clk", - .pid = SAMA5D3_ID_DMA1, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk uhphs_clk = { - .name = "uhphs", - .pid = SAMA5D3_ID_UHPHS, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk udphs_clk = { - .name = "udphs_clk", - .pid = SAMA5D3_ID_UDPHS, - .type = CLK_TYPE_PERIPHERAL, -}; -/* gmac only for sama5d33, sama5d34, sama5d35 */ -static struct clk macb0_clk = { - .name = "macb0_clk", - .pid = SAMA5D3_ID_GMAC, - .type = CLK_TYPE_PERIPHERAL, -}; -/* emac only for sama5d31, sama5d35 */ -static struct clk macb1_clk = { - .name = "macb1_clk", - .pid = SAMA5D3_ID_EMAC, - .type = CLK_TYPE_PERIPHERAL, -}; -/* lcd only for sama5d31, sama5d33, sama5d34 */ -static struct clk lcdc_clk = { - .name = "lcdc_clk", - .pid = SAMA5D3_ID_LCDC, - .type = CLK_TYPE_PERIPHERAL, -}; -/* isi only for sama5d33, sama5d35 */ -static struct clk isi_clk = { - .name = "isi_clk", - .pid = SAMA5D3_ID_ISI, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk can0_clk = { - .name = "can0_clk", - .pid = SAMA5D3_ID_CAN0, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV2, -}; -static struct clk can1_clk = { - .name = "can1_clk", - .pid = SAMA5D3_ID_CAN1, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV2, -}; -static struct clk ssc0_clk = { - .name = "ssc0_clk", - .pid = SAMA5D3_ID_SSC0, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV2, -}; -static struct clk ssc1_clk = { - .name = "ssc1_clk", - .pid = SAMA5D3_ID_SSC1, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV2, -}; -static struct clk sha_clk = { - .name = "sha_clk", - .pid = SAMA5D3_ID_SHA, - .type = CLK_TYPE_PERIPHERAL, - .div = AT91_PMC_PCR_DIV8, -}; -static struct clk aes_clk = { - .name = "aes_clk", - .pid = SAMA5D3_ID_AES, - .type = CLK_TYPE_PERIPHERAL, -}; -static struct clk tdes_clk = { - .name = "tdes_clk", - .pid = SAMA5D3_ID_TDES, - .type = CLK_TYPE_PERIPHERAL, -}; - -static struct clk *periph_clocks[] __initdata = { - &pioA_clk, - &pioB_clk, - &pioC_clk, - &pioD_clk, - &pioE_clk, - &usart0_clk, - &usart1_clk, - &usart2_clk, - &usart3_clk, - &uart0_clk, - &uart1_clk, - &twi0_clk, - &twi1_clk, - &twi2_clk, - &mmc0_clk, - &mmc1_clk, - &mmc2_clk, - &spi0_clk, - &spi1_clk, - &tcb0_clk, - &tcb1_clk, - &adc_clk, - &adc_op_clk, - &dma0_clk, - &dma1_clk, - &uhphs_clk, - &udphs_clk, - &macb0_clk, - &macb1_clk, - &lcdc_clk, - &isi_clk, - &can0_clk, - &can1_clk, - &ssc0_clk, - &ssc1_clk, - &sha_clk, - &aes_clk, - &tdes_clk, -}; - -static struct clk pck0 = { - .name = "pck0", - .pmc_mask = AT91_PMC_PCK0, - .type = CLK_TYPE_PROGRAMMABLE, - .id = 0, -}; - -static struct clk pck1 = { - .name = "pck1", - .pmc_mask = AT91_PMC_PCK1, - .type = CLK_TYPE_PROGRAMMABLE, - .id = 1, -}; - -static struct clk pck2 = { - .name = "pck2", - .pmc_mask = AT91_PMC_PCK2, - .type = CLK_TYPE_PROGRAMMABLE, - .id = 2, -}; - -static struct clk_lookup periph_clocks_lookups[] = { - /* lookup table for DT entries */ - CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck), - CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk), - CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk), - CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk), - CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioD_clk), - CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioE_clk), - CLKDEV_CON_DEV_ID("usart", "f001c000.serial", &usart0_clk), - CLKDEV_CON_DEV_ID("usart", "f0020000.serial", &usart1_clk), - CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart2_clk), - CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart3_clk), - CLKDEV_CON_DEV_ID(NULL, "f0014000.i2c", &twi0_clk), - CLKDEV_CON_DEV_ID(NULL, "f0018000.i2c", &twi1_clk), - CLKDEV_CON_DEV_ID(NULL, "f801c000.i2c", &twi2_clk), - CLKDEV_CON_DEV_ID("mci_clk", "f0000000.mmc", &mmc0_clk), - CLKDEV_CON_DEV_ID("mci_clk", "f8000000.mmc", &mmc1_clk), - CLKDEV_CON_DEV_ID("mci_clk", "f8004000.mmc", &mmc2_clk), - CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi0_clk), - CLKDEV_CON_DEV_ID("spi_clk", "f8008000.spi", &spi1_clk), - CLKDEV_CON_DEV_ID("t0_clk", "f0010000.timer", &tcb0_clk), - CLKDEV_CON_DEV_ID("t0_clk", "f8014000.timer", &tcb1_clk), - CLKDEV_CON_DEV_ID("tsc_clk", "f8018000.tsadcc", &adc_clk), - CLKDEV_CON_DEV_ID("dma_clk", "ffffe600.dma-controller", &dma0_clk), - CLKDEV_CON_DEV_ID("dma_clk", "ffffe800.dma-controller", &dma1_clk), - CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk), - CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk), - CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk), - CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk), - CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk), - CLKDEV_CON_DEV_ID("hclk", "f0028000.ethernet", &macb0_clk), - CLKDEV_CON_DEV_ID("pclk", "f0028000.ethernet", &macb0_clk), - CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb1_clk), - CLKDEV_CON_DEV_ID("pclk", "f802c000.ethernet", &macb1_clk), - CLKDEV_CON_DEV_ID("pclk", "f0008000.ssc", &ssc0_clk), - CLKDEV_CON_DEV_ID("pclk", "f000c000.ssc", &ssc1_clk), - CLKDEV_CON_DEV_ID("can_clk", "f000c000.can", &can0_clk), - CLKDEV_CON_DEV_ID("can_clk", "f8010000.can", &can1_clk), - CLKDEV_CON_DEV_ID("sha_clk", "f8034000.sha", &sha_clk), - CLKDEV_CON_DEV_ID("aes_clk", "f8038000.aes", &aes_clk), - CLKDEV_CON_DEV_ID("tdes_clk", "f803c000.tdes", &tdes_clk), -}; - -static void __init sama5d3_register_clocks(void) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) - clk_register(periph_clocks[i]); - - clkdev_add_table(periph_clocks_lookups, - ARRAY_SIZE(periph_clocks_lookups)); - - clk_register(&pck0); - clk_register(&pck1); - clk_register(&pck2); -} - -/* -------------------------------------------------------------------- * AT91SAM9x5 processor initialization * -------------------------------------------------------------------- */ @@ -378,6 +37,5 @@ static void __init sama5d3_initialize(void) AT91_SOC_START(sama5d3) .map_io = sama5d3_map_io, - .register_clocks = sama5d3_register_clocks, .init = sama5d3_initialize, AT91_SOC_END diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c index 2742e00ec5d6..9dc8894c5623 100644 --- a/arch/arm/mach-at91/setup.c +++ b/arch/arm/mach-at91/setup.c @@ -11,6 +11,7 @@ #include <linux/pm.h> #include <linux/of_address.h> #include <linux/pinctrl/machine.h> +#include <linux/clk/at91_pmc.h> #include <asm/system_misc.h> #include <asm/mach/map.h> @@ -18,7 +19,6 @@ #include <mach/hardware.h> #include <mach/cpu.h> #include <mach/at91_dbgu.h> -#include <mach/at91_pmc.h> #include "at91_shdwc.h" #include "soc.h" @@ -491,7 +491,8 @@ void __init at91rm9200_dt_initialize(void) at91_dt_clock_init(); /* Register the processor-specific clocks */ - at91_boot_soc.register_clocks(); + if (at91_boot_soc.register_clocks) + at91_boot_soc.register_clocks(); at91_boot_soc.init(); } @@ -506,7 +507,8 @@ void __init at91_dt_initialize(void) at91_dt_clock_init(); /* Register the processor-specific clocks */ - at91_boot_soc.register_clocks(); + if (at91_boot_soc.register_clocks) + at91_boot_soc.register_clocks(); if (at91_boot_soc.init) at91_boot_soc.init(); diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c index c122bcff9f7c..0d1a89298ece 100644 --- a/arch/arm/mach-dove/common.c +++ b/arch/arm/mach-dove/common.c @@ -162,7 +162,7 @@ void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data) /***************************************************************************** * SoC RTC ****************************************************************************/ -void __init dove_rtc_init(void) +static void __init dove_rtc_init(void) { orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC); } @@ -257,18 +257,9 @@ void __init dove_timer_init(void) } /***************************************************************************** - * Cryptographic Engines and Security Accelerator (CESA) - ****************************************************************************/ -void __init dove_crypto_init(void) -{ - orion_crypto_init(DOVE_CRYPT_PHYS_BASE, DOVE_CESA_PHYS_BASE, - DOVE_CESA_SIZE, IRQ_DOVE_CRYPTO); -} - -/***************************************************************************** * XOR 0 ****************************************************************************/ -void __init dove_xor0_init(void) +static void __init dove_xor0_init(void) { orion_xor0_init(DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE, IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01); @@ -277,7 +268,7 @@ void __init dove_xor0_init(void) /***************************************************************************** * XOR 1 ****************************************************************************/ -void __init dove_xor1_init(void) +static void __init dove_xor1_init(void) { orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE, IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11); diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index f9d67a0acb2a..4c414af75ef0 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -24,6 +24,7 @@ config ARCH_EXYNOS4 select HAVE_SMP select MIGHT_HAVE_CACHE_L2X0 select PINCTRL + select PM_GENERIC_DOMAINS if PM select S5P_DEV_MFC help Samsung EXYNOS4 SoCs based systems @@ -48,7 +49,6 @@ config CPU_EXYNOS4210 select ARCH_HAS_BANDGAP select ARM_CPU_SUSPEND if PM select PINCTRL_EXYNOS - select PM_GENERIC_DOMAINS if PM select S5P_PM if PM select S5P_SLEEP if PM select SAMSUNG_DMADEV @@ -61,7 +61,6 @@ config SOC_EXYNOS4212 depends on ARCH_EXYNOS4 select ARCH_HAS_BANDGAP select PINCTRL_EXYNOS - select PM_GENERIC_DOMAINS if PM select S5P_PM if PM select S5P_SLEEP if PM select SAMSUNG_DMADEV @@ -74,7 +73,6 @@ config SOC_EXYNOS4412 depends on ARCH_EXYNOS4 select ARCH_HAS_BANDGAP select PINCTRL_EXYNOS - select PM_GENERIC_DOMAINS if PM select SAMSUNG_DMADEV help Enable EXYNOS4412 SoC support diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index 61d2906ccefb..72ae5d3a87d2 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -23,6 +23,7 @@ #include <linux/of.h> #include <linux/of_fdt.h> #include <linux/of_irq.h> +#include <linux/pm_domain.h> #include <linux/export.h> #include <linux/irqdomain.h> #include <linux/of_address.h> @@ -37,14 +38,13 @@ #include <asm/mach/irq.h> #include <asm/cacheflush.h> -#include <mach/regs-irq.h> -#include <mach/regs-pmu.h> - #include <plat/cpu.h> #include <plat/pm.h> #include <plat/regs-serial.h> #include "common.h" +#include "regs-pmu.h" + #define L2_AUX_VAL 0x7C470001 #define L2_AUX_MASK 0xC200ffff @@ -309,7 +309,7 @@ void __init exynos_init_late(void) /* to be supported later */ return; - exynos_pm_late_initcall(); + pm_genpd_poweroff_unused(); } static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname, diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index ff9b6a9419b0..0c31b34f0de5 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -26,12 +26,6 @@ void exynos_init_late(void); void exynos_firmware_init(void); -#ifdef CONFIG_PM_GENERIC_DOMAINS -int exynos_pm_late_initcall(void); -#else -static inline int exynos_pm_late_initcall(void) { return 0; } -#endif - extern struct smp_operations exynos_smp_ops; extern void exynos_cpu_die(unsigned int cpu); diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c index ddbfe8709fe7..da65b036af2b 100644 --- a/arch/arm/mach-exynos/cpuidle.c +++ b/arch/arm/mach-exynos/cpuidle.c @@ -22,13 +22,15 @@ #include <asm/suspend.h> #include <asm/unified.h> #include <asm/cpuidle.h> -#include <mach/regs-clock.h> -#include <mach/regs-pmu.h> #include <plat/cpu.h> #include <plat/pm.h> +#include <mach/pm-core.h> +#include <mach/map.h> + #include "common.h" +#include "regs-pmu.h" #define REG_DIRECTGO_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \ S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ @@ -39,6 +41,25 @@ #define S5P_CHECK_AFTR 0xFCBA0D10 +#define EXYNOS5_PWR_CTRL1 (S5P_VA_CMU + 0x01020) +#define EXYNOS5_PWR_CTRL2 (S5P_VA_CMU + 0x01024) + +#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28) +#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16) +#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9) +#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8) +#define PWR_CTRL1_USE_CORE1_WFE (1 << 5) +#define PWR_CTRL1_USE_CORE0_WFE (1 << 4) +#define PWR_CTRL1_USE_CORE1_WFI (1 << 1) +#define PWR_CTRL1_USE_CORE0_WFI (1 << 0) + +#define PWR_CTRL2_DIV2_UP_EN (1 << 25) +#define PWR_CTRL2_DIV1_UP_EN (1 << 24) +#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16) +#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8) +#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4) +#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0) + static int exynos4_enter_lowpower(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index); diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c index af90cfa2f826..5eead530c6f8 100644 --- a/arch/arm/mach-exynos/hotplug.c +++ b/arch/arm/mach-exynos/hotplug.c @@ -19,10 +19,10 @@ #include <asm/cp15.h> #include <asm/smp_plat.h> -#include <mach/regs-pmu.h> #include <plat/cpu.h> #include "common.h" +#include "regs-pmu.h" static inline void cpu_enter_lowpower_a9(void) { diff --git a/arch/arm/mach-exynos/include/mach/pm-core.h b/arch/arm/mach-exynos/include/mach/pm-core.h index 2b00833b6641..dc0697c2fa92 100644 --- a/arch/arm/mach-exynos/include/mach/pm-core.h +++ b/arch/arm/mach-exynos/include/mach/pm-core.h @@ -19,7 +19,10 @@ #define __ASM_ARCH_PM_CORE_H __FILE__ #include <linux/of.h> -#include <mach/regs-pmu.h> +#include <mach/map.h> + +#define S5P_EINT_WAKEUP_MASK (S5P_VA_PMU + 0x0604) +#define S5P_WAKEUP_MASK (S5P_VA_PMU + 0x0608) #ifdef CONFIG_PINCTRL_EXYNOS extern u32 exynos_get_eint_wake_mask(void); diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h deleted file mode 100644 index d36ad76ad6a4..000000000000 --- a/arch/arm/mach-exynos/include/mach/regs-clock.h +++ /dev/null @@ -1,372 +0,0 @@ -/* linux/arch/arm/mach-exynos4/include/mach/regs-clock.h - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS4 - Clock register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_REGS_CLOCK_H -#define __ASM_ARCH_REGS_CLOCK_H __FILE__ - -#include <plat/cpu.h> -#include <mach/map.h> - -#define EXYNOS_CLKREG(x) (S5P_VA_CMU + (x)) - -#define EXYNOS4_CLKDIV_LEFTBUS EXYNOS_CLKREG(0x04500) -#define EXYNOS4_CLKDIV_STAT_LEFTBUS EXYNOS_CLKREG(0x04600) -#define EXYNOS4_CLKGATE_IP_LEFTBUS EXYNOS_CLKREG(0x04800) - -#define EXYNOS4_CLKDIV_RIGHTBUS EXYNOS_CLKREG(0x08500) -#define EXYNOS4_CLKDIV_STAT_RIGHTBUS EXYNOS_CLKREG(0x08600) -#define EXYNOS4_CLKGATE_IP_RIGHTBUS EXYNOS_CLKREG(0x08800) - -#define EXYNOS4_EPLL_LOCK EXYNOS_CLKREG(0x0C010) -#define EXYNOS4_VPLL_LOCK EXYNOS_CLKREG(0x0C020) - -#define EXYNOS4_EPLL_CON0 EXYNOS_CLKREG(0x0C110) -#define EXYNOS4_EPLL_CON1 EXYNOS_CLKREG(0x0C114) -#define EXYNOS4_VPLL_CON0 EXYNOS_CLKREG(0x0C120) -#define EXYNOS4_VPLL_CON1 EXYNOS_CLKREG(0x0C124) - -#define EXYNOS4_CLKSRC_TOP0 EXYNOS_CLKREG(0x0C210) -#define EXYNOS4_CLKSRC_TOP1 EXYNOS_CLKREG(0x0C214) -#define EXYNOS4_CLKSRC_CAM EXYNOS_CLKREG(0x0C220) -#define EXYNOS4_CLKSRC_TV EXYNOS_CLKREG(0x0C224) -#define EXYNOS4_CLKSRC_MFC EXYNOS_CLKREG(0x0C228) -#define EXYNOS4_CLKSRC_G3D EXYNOS_CLKREG(0x0C22C) -#define EXYNOS4_CLKSRC_IMAGE EXYNOS_CLKREG(0x0C230) -#define EXYNOS4_CLKSRC_LCD0 EXYNOS_CLKREG(0x0C234) -#define EXYNOS4_CLKSRC_MAUDIO EXYNOS_CLKREG(0x0C23C) -#define EXYNOS4_CLKSRC_FSYS EXYNOS_CLKREG(0x0C240) -#define EXYNOS4_CLKSRC_PERIL0 EXYNOS_CLKREG(0x0C250) -#define EXYNOS4_CLKSRC_PERIL1 EXYNOS_CLKREG(0x0C254) - -#define EXYNOS4_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x0C310) -#define EXYNOS4_CLKSRC_MASK_CAM EXYNOS_CLKREG(0x0C320) -#define EXYNOS4_CLKSRC_MASK_TV EXYNOS_CLKREG(0x0C324) -#define EXYNOS4_CLKSRC_MASK_LCD0 EXYNOS_CLKREG(0x0C334) -#define EXYNOS4_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x0C33C) -#define EXYNOS4_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x0C340) -#define EXYNOS4_CLKSRC_MASK_PERIL0 EXYNOS_CLKREG(0x0C350) -#define EXYNOS4_CLKSRC_MASK_PERIL1 EXYNOS_CLKREG(0x0C354) - -#define EXYNOS4_CLKDIV_TOP EXYNOS_CLKREG(0x0C510) -#define EXYNOS4_CLKDIV_CAM EXYNOS_CLKREG(0x0C520) -#define EXYNOS4_CLKDIV_TV EXYNOS_CLKREG(0x0C524) -#define EXYNOS4_CLKDIV_MFC EXYNOS_CLKREG(0x0C528) -#define EXYNOS4_CLKDIV_G3D EXYNOS_CLKREG(0x0C52C) -#define EXYNOS4_CLKDIV_IMAGE EXYNOS_CLKREG(0x0C530) -#define EXYNOS4_CLKDIV_LCD0 EXYNOS_CLKREG(0x0C534) -#define EXYNOS4_CLKDIV_MAUDIO EXYNOS_CLKREG(0x0C53C) -#define EXYNOS4_CLKDIV_FSYS0 EXYNOS_CLKREG(0x0C540) -#define EXYNOS4_CLKDIV_FSYS1 EXYNOS_CLKREG(0x0C544) -#define EXYNOS4_CLKDIV_FSYS2 EXYNOS_CLKREG(0x0C548) -#define EXYNOS4_CLKDIV_FSYS3 EXYNOS_CLKREG(0x0C54C) -#define EXYNOS4_CLKDIV_PERIL0 EXYNOS_CLKREG(0x0C550) -#define EXYNOS4_CLKDIV_PERIL1 EXYNOS_CLKREG(0x0C554) -#define EXYNOS4_CLKDIV_PERIL2 EXYNOS_CLKREG(0x0C558) -#define EXYNOS4_CLKDIV_PERIL3 EXYNOS_CLKREG(0x0C55C) -#define EXYNOS4_CLKDIV_PERIL4 EXYNOS_CLKREG(0x0C560) -#define EXYNOS4_CLKDIV_PERIL5 EXYNOS_CLKREG(0x0C564) -#define EXYNOS4_CLKDIV2_RATIO EXYNOS_CLKREG(0x0C580) - -#define EXYNOS4_CLKDIV_STAT_TOP EXYNOS_CLKREG(0x0C610) -#define EXYNOS4_CLKDIV_STAT_MFC EXYNOS_CLKREG(0x0C628) - -#define EXYNOS4_CLKGATE_SCLKCAM EXYNOS_CLKREG(0x0C820) -#define EXYNOS4_CLKGATE_IP_CAM EXYNOS_CLKREG(0x0C920) -#define EXYNOS4_CLKGATE_IP_TV EXYNOS_CLKREG(0x0C924) -#define EXYNOS4_CLKGATE_IP_MFC EXYNOS_CLKREG(0x0C928) -#define EXYNOS4_CLKGATE_IP_G3D EXYNOS_CLKREG(0x0C92C) -#define EXYNOS4_CLKGATE_IP_IMAGE (soc_is_exynos4210() ? \ - EXYNOS_CLKREG(0x0C930) : \ - EXYNOS_CLKREG(0x04930)) -#define EXYNOS4210_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x0C930) -#define EXYNOS4212_CLKGATE_IP_IMAGE EXYNOS_CLKREG(0x04930) -#define EXYNOS4_CLKGATE_IP_LCD0 EXYNOS_CLKREG(0x0C934) -#define EXYNOS4_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x0C940) -#define EXYNOS4_CLKGATE_IP_GPS EXYNOS_CLKREG(0x0C94C) -#define EXYNOS4_CLKGATE_IP_PERIL EXYNOS_CLKREG(0x0C950) -#define EXYNOS4_CLKGATE_IP_PERIR (soc_is_exynos4210() ? \ - EXYNOS_CLKREG(0x0C960) : \ - EXYNOS_CLKREG(0x08960)) -#define EXYNOS4210_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x0C960) -#define EXYNOS4212_CLKGATE_IP_PERIR EXYNOS_CLKREG(0x08960) -#define EXYNOS4_CLKGATE_BLOCK EXYNOS_CLKREG(0x0C970) - -#define EXYNOS4_CLKSRC_MASK_DMC EXYNOS_CLKREG(0x10300) -#define EXYNOS4_CLKSRC_DMC EXYNOS_CLKREG(0x10200) -#define EXYNOS4_CLKDIV_DMC0 EXYNOS_CLKREG(0x10500) -#define EXYNOS4_CLKDIV_DMC1 EXYNOS_CLKREG(0x10504) -#define EXYNOS4_CLKDIV_STAT_DMC0 EXYNOS_CLKREG(0x10600) -#define EXYNOS4_CLKDIV_STAT_DMC1 EXYNOS_CLKREG(0x10604) -#define EXYNOS4_CLKGATE_IP_DMC EXYNOS_CLKREG(0x10900) - -#define EXYNOS4_DMC_PAUSE_CTRL EXYNOS_CLKREG(0x11094) -#define EXYNOS4_DMC_PAUSE_ENABLE (1 << 0) - -#define EXYNOS4_APLL_LOCK EXYNOS_CLKREG(0x14000) -#define EXYNOS4_MPLL_LOCK (soc_is_exynos4210() ? \ - EXYNOS_CLKREG(0x14004) : \ - EXYNOS_CLKREG(0x10008)) -#define EXYNOS4_APLL_CON0 EXYNOS_CLKREG(0x14100) -#define EXYNOS4_APLL_CON1 EXYNOS_CLKREG(0x14104) -#define EXYNOS4_MPLL_CON0 (soc_is_exynos4210() ? \ - EXYNOS_CLKREG(0x14108) : \ - EXYNOS_CLKREG(0x10108)) -#define EXYNOS4_MPLL_CON1 (soc_is_exynos4210() ? \ - EXYNOS_CLKREG(0x1410C) : \ - EXYNOS_CLKREG(0x1010C)) - -#define EXYNOS4_CLKSRC_CPU EXYNOS_CLKREG(0x14200) -#define EXYNOS4_CLKMUX_STATCPU EXYNOS_CLKREG(0x14400) - -#define EXYNOS4_CLKDIV_CPU EXYNOS_CLKREG(0x14500) -#define EXYNOS4_CLKDIV_CPU1 EXYNOS_CLKREG(0x14504) -#define EXYNOS4_CLKDIV_STATCPU EXYNOS_CLKREG(0x14600) -#define EXYNOS4_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x14604) - -#define EXYNOS4_CLKGATE_SCLKCPU EXYNOS_CLKREG(0x14800) -#define EXYNOS4_CLKGATE_IP_CPU EXYNOS_CLKREG(0x14900) - -#define EXYNOS4_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x18800) -#define EXYNOS4_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x18804) - -#define EXYNOS4_APLL_LOCKTIME (0x1C20) /* 300us */ - -#define EXYNOS4_APLLCON0_ENABLE_SHIFT (31) -#define EXYNOS4_APLLCON0_LOCKED_SHIFT (29) -#define EXYNOS4_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1) -#define EXYNOS4_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1) - -#define EXYNOS4_EPLLCON0_ENABLE_SHIFT (31) -#define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29) - -#define EXYNOS4_VPLLCON0_ENABLE_SHIFT (31) -#define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29) - -#define EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT (16) -#define EXYNOS4_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << EXYNOS4_CLKSRC_CPU_MUXCORE_SHIFT) - -#define EXYNOS4_CLKDIV_CPU0_CORE_SHIFT (0) -#define EXYNOS4_CLKDIV_CPU0_CORE_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) -#define EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT (4) -#define EXYNOS4_CLKDIV_CPU0_COREM0_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) -#define EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT (8) -#define EXYNOS4_CLKDIV_CPU0_COREM1_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) -#define EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT (12) -#define EXYNOS4_CLKDIV_CPU0_PERIPH_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) -#define EXYNOS4_CLKDIV_CPU0_ATB_SHIFT (16) -#define EXYNOS4_CLKDIV_CPU0_ATB_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) -#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT (20) -#define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) -#define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT (24) -#define EXYNOS4_CLKDIV_CPU0_APLL_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT) -#define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT 28 -#define EXYNOS4_CLKDIV_CPU0_CORE2_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT) - -#define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT 0 -#define EXYNOS4_CLKDIV_CPU1_COPY_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT) -#define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT 4 -#define EXYNOS4_CLKDIV_CPU1_HPM_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT) -#define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT 8 -#define EXYNOS4_CLKDIV_CPU1_CORES_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT) - -#define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0) -#define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4) -#define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8) -#define EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12) -#define EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16) -#define EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20) -#define EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24) -#define EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT) -#define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28) -#define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT) - -#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT (0) -#define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT) -#define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT (4) -#define EXYNOS4_CLKDIV_DMC1_C2C_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT) -#define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT (8) -#define EXYNOS4_CLKDIV_DMC1_PWI_MASK (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT) -#define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT (12) -#define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT) -#define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT (16) -#define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT) -#define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT (24) -#define EXYNOS4_CLKDIV_DMC1_DPM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT) - -#define EXYNOS4_CLKDIV_MFC_SHIFT (0) -#define EXYNOS4_CLKDIV_MFC_MASK (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT) - -#define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0) -#define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT) -#define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4) -#define EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) -#define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8) -#define EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) -#define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12) -#define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) -#define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16) -#define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT) -#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT (20) -#define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT) -#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24) -#define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT) - -#define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0) -#define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) -#define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4) -#define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT) - -#define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT (0) -#define EXYNOS4_CLKDIV_CAM_FIMC0_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT) -#define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT (4) -#define EXYNOS4_CLKDIV_CAM_FIMC1_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT) -#define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT (8) -#define EXYNOS4_CLKDIV_CAM_FIMC2_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT) -#define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT (12) -#define EXYNOS4_CLKDIV_CAM_FIMC3_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT) - -/* Only for EXYNOS4210 */ - -#define EXYNOS4210_CLKSRC_LCD1 EXYNOS_CLKREG(0x0C238) -#define EXYNOS4210_CLKSRC_MASK_LCD1 EXYNOS_CLKREG(0x0C338) -#define EXYNOS4210_CLKDIV_LCD1 EXYNOS_CLKREG(0x0C538) -#define EXYNOS4210_CLKGATE_IP_LCD1 EXYNOS_CLKREG(0x0C938) - -/* Only for EXYNOS4212 */ - -#define EXYNOS4_CLKDIV_CAM1 EXYNOS_CLKREG(0x0C568) - -#define EXYNOS4_CLKDIV_STAT_CAM1 EXYNOS_CLKREG(0x0C668) - -#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0) -#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT) - -/* For EXYNOS5250 */ - -#define EXYNOS5_APLL_LOCK EXYNOS_CLKREG(0x00000) -#define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100) -#define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200) -#define EXYNOS5_CLKMUX_STATCPU EXYNOS_CLKREG(0x00400) -#define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500) -#define EXYNOS5_CLKDIV_CPU1 EXYNOS_CLKREG(0x00504) -#define EXYNOS5_CLKDIV_STATCPU0 EXYNOS_CLKREG(0x00600) -#define EXYNOS5_CLKDIV_STATCPU1 EXYNOS_CLKREG(0x00604) - -#define EXYNOS5_PWR_CTRL1 EXYNOS_CLKREG(0x01020) -#define EXYNOS5_PWR_CTRL2 EXYNOS_CLKREG(0x01024) - -#define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100) -#define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204) - -#define EXYNOS5_CLKGATE_IP_CORE EXYNOS_CLKREG(0x04900) - -#define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500) - -#define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130) -#define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134) -#define EXYNOS5_EPLL_CON2 EXYNOS_CLKREG(0x10138) -#define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140) -#define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144) -#define EXYNOS5_VPLL_CON2 EXYNOS_CLKREG(0x10148) -#define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120) - -#define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210) -#define EXYNOS5_CLKSRC_TOP1 EXYNOS_CLKREG(0x10214) -#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218) -#define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C) -#define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220) -#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C) -#define EXYNOS5_CLKSRC_MAUDIO EXYNOS_CLKREG(0x10240) -#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244) -#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250) -#define EXYNOS5_CLKSRC_PERIC1 EXYNOS_CLKREG(0x10254) -#define EXYNOS5_SCLK_SRC_ISP EXYNOS_CLKREG(0x10270) - -#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310) -#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320) -#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C) -#define EXYNOS5_CLKSRC_MASK_MAUDIO EXYNOS_CLKREG(0x10334) -#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340) -#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350) -#define EXYNOS5_CLKSRC_MASK_PERIC1 EXYNOS_CLKREG(0x10354) - -#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510) -#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514) -#define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520) -#define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C) -#define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C) -#define EXYNOS5_CLKDIV_MAUDIO EXYNOS_CLKREG(0x10544) -#define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548) -#define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C) -#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550) -#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554) -#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558) -#define EXYNOS5_CLKDIV_PERIC1 EXYNOS_CLKREG(0x1055C) -#define EXYNOS5_CLKDIV_PERIC2 EXYNOS_CLKREG(0x10560) -#define EXYNOS5_CLKDIV_PERIC3 EXYNOS_CLKREG(0x10564) -#define EXYNOS5_CLKDIV_PERIC4 EXYNOS_CLKREG(0x10568) -#define EXYNOS5_CLKDIV_PERIC5 EXYNOS_CLKREG(0x1056C) -#define EXYNOS5_SCLK_DIV_ISP EXYNOS_CLKREG(0x10580) - -#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800) -#define EXYNOS5_CLKGATE_IP_ISP0 EXYNOS_CLKREG(0x0C800) -#define EXYNOS5_CLKGATE_IP_ISP1 EXYNOS_CLKREG(0x0C804) -#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920) -#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928) -#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C) -#define EXYNOS5_CLKGATE_IP_G3D EXYNOS_CLKREG(0x10930) -#define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934) -#define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944) -#define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C) -#define EXYNOS5_CLKGATE_IP_PERIC EXYNOS_CLKREG(0x10950) -#define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960) -#define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980) - -#define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110) -#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200) -#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500) - -#define EXYNOS5_PLL_DIV2_SEL EXYNOS_CLKREG(0x20A24) - -#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030) - -#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29) - -#define PWR_CTRL1_CORE2_DOWN_RATIO (7 << 28) -#define PWR_CTRL1_CORE1_DOWN_RATIO (7 << 16) -#define PWR_CTRL1_DIV2_DOWN_EN (1 << 9) -#define PWR_CTRL1_DIV1_DOWN_EN (1 << 8) -#define PWR_CTRL1_USE_CORE1_WFE (1 << 5) -#define PWR_CTRL1_USE_CORE0_WFE (1 << 4) -#define PWR_CTRL1_USE_CORE1_WFI (1 << 1) -#define PWR_CTRL1_USE_CORE0_WFI (1 << 0) - -#define PWR_CTRL2_DIV2_UP_EN (1 << 25) -#define PWR_CTRL2_DIV1_UP_EN (1 << 24) -#define PWR_CTRL2_DUR_STANDBY2_VAL (1 << 16) -#define PWR_CTRL2_DUR_STANDBY1_VAL (1 << 8) -#define PWR_CTRL2_CORE2_UP_RATIO (1 << 4) -#define PWR_CTRL2_CORE1_UP_RATIO (1 << 0) - -/* Compatibility defines and inclusion */ - -#include <mach/regs-pmu.h> - -#define S5P_EPLL_CON EXYNOS4_EPLL_CON0 - -#endif /* __ASM_ARCH_REGS_CLOCK_H */ diff --git a/arch/arm/mach-exynos/include/mach/regs-irq.h b/arch/arm/mach-exynos/include/mach/regs-irq.h deleted file mode 100644 index f2b50506b9f6..000000000000 --- a/arch/arm/mach-exynos/include/mach/regs-irq.h +++ /dev/null @@ -1,19 +0,0 @@ -/* linux/arch/arm/mach-exynos4/include/mach/regs-irq.h - * - * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS4 - IRQ register definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_REGS_IRQ_H -#define __ASM_ARCH_REGS_IRQ_H __FILE__ - -#include <linux/irqchip/arm-gic.h> -#include <mach/map.h> - -#endif /* __ASM_ARCH_REGS_IRQ_H */ diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c index 1fe075a70c1e..65a46465ac5e 100644 --- a/arch/arm/mach-exynos/mach-exynos5-dt.c +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c @@ -14,10 +14,10 @@ #include <linux/io.h> #include <asm/mach/arch.h> -#include <mach/regs-pmu.h> #include <plat/mfc.h> #include "common.h" +#include "regs-pmu.h" static void __init exynos5_dt_machine_init(void) { diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index 58b43e6f9262..8ea02f63fed9 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -27,12 +27,11 @@ #include <asm/firmware.h> #include <mach/hardware.h> -#include <mach/regs-clock.h> -#include <mach/regs-pmu.h> #include <plat/cpu.h> #include "common.h" +#include "regs-pmu.h" extern void exynos4_secondary_startup(void); @@ -64,8 +63,7 @@ static void write_pen_release(int val) { pen_release = val; smp_wmb(); - __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); - outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); + sync_cache_w(&pen_release); } static void __iomem *scu_base_addr(void) diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index c679db577269..e00025bbbe89 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -29,14 +29,37 @@ #include <plat/pll.h> #include <plat/regs-srom.h> -#include <mach/regs-irq.h> -#include <mach/regs-clock.h> -#include <mach/regs-pmu.h> +#include <mach/map.h> #include <mach/pm-core.h> #include "common.h" +#include "regs-pmu.h" -static struct sleep_save exynos4_set_clksrc[] = { +#define EXYNOS4_EPLL_LOCK (S5P_VA_CMU + 0x0C010) +#define EXYNOS4_VPLL_LOCK (S5P_VA_CMU + 0x0C020) + +#define EXYNOS4_EPLL_CON0 (S5P_VA_CMU + 0x0C110) +#define EXYNOS4_EPLL_CON1 (S5P_VA_CMU + 0x0C114) +#define EXYNOS4_VPLL_CON0 (S5P_VA_CMU + 0x0C120) +#define EXYNOS4_VPLL_CON1 (S5P_VA_CMU + 0x0C124) + +#define EXYNOS4_CLKSRC_MASK_TOP (S5P_VA_CMU + 0x0C310) +#define EXYNOS4_CLKSRC_MASK_CAM (S5P_VA_CMU + 0x0C320) +#define EXYNOS4_CLKSRC_MASK_TV (S5P_VA_CMU + 0x0C324) +#define EXYNOS4_CLKSRC_MASK_LCD0 (S5P_VA_CMU + 0x0C334) +#define EXYNOS4_CLKSRC_MASK_MAUDIO (S5P_VA_CMU + 0x0C33C) +#define EXYNOS4_CLKSRC_MASK_FSYS (S5P_VA_CMU + 0x0C340) +#define EXYNOS4_CLKSRC_MASK_PERIL0 (S5P_VA_CMU + 0x0C350) +#define EXYNOS4_CLKSRC_MASK_PERIL1 (S5P_VA_CMU + 0x0C354) + +#define EXYNOS4_CLKSRC_MASK_DMC (S5P_VA_CMU + 0x10300) + +#define EXYNOS4_EPLLCON0_LOCKED_SHIFT (29) +#define EXYNOS4_VPLLCON0_LOCKED_SHIFT (29) + +#define EXYNOS4210_CLKSRC_MASK_LCD1 (S5P_VA_CMU + 0x0C338) + +static const struct sleep_save exynos4_set_clksrc[] = { { .reg = EXYNOS4_CLKSRC_MASK_TOP , .val = 0x00000001, }, { .reg = EXYNOS4_CLKSRC_MASK_CAM , .val = 0x11111111, }, { .reg = EXYNOS4_CLKSRC_MASK_TV , .val = 0x00000111, }, @@ -48,7 +71,7 @@ static struct sleep_save exynos4_set_clksrc[] = { { .reg = EXYNOS4_CLKSRC_MASK_DMC , .val = 0x00010000, }, }; -static struct sleep_save exynos4210_set_clksrc[] = { +static const struct sleep_save exynos4210_set_clksrc[] = { { .reg = EXYNOS4210_CLKSRC_MASK_LCD1 , .val = 0x00001111, }, }; diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c index 1703593e366c..8fd24882f0b1 100644 --- a/arch/arm/mach-exynos/pm_domains.c +++ b/arch/arm/mach-exynos/pm_domains.c @@ -22,9 +22,10 @@ #include <linux/of_platform.h> #include <linux/sched.h> -#include <mach/regs-pmu.h> #include <plat/devs.h> +#include "regs-pmu.h" + /* * Exynos specific wrapper around the generic power domain */ @@ -183,9 +184,3 @@ static __init int exynos4_pm_init_power_domain(void) return 0; } arch_initcall(exynos4_pm_init_power_domain); - -int __init exynos_pm_late_initcall(void) -{ - pm_genpd_poweroff_unused(); - return 0; -} diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c index 97d688526258..05c7ce15322a 100644 --- a/arch/arm/mach-exynos/pmu.c +++ b/arch/arm/mach-exynos/pmu.c @@ -13,13 +13,14 @@ #include <linux/kernel.h> #include <linux/bug.h> -#include <mach/regs-clock.h> +#include <plat/cpu.h> #include "common.h" +#include "regs-pmu.h" -static struct exynos_pmu_conf *exynos_pmu_config; +static const struct exynos_pmu_conf *exynos_pmu_config; -static struct exynos_pmu_conf exynos4210_pmu_config[] = { +static const struct exynos_pmu_conf exynos4210_pmu_config[] = { /* { .reg = address, .val = { AFTR, LPA, SLEEP } */ { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, @@ -95,7 +96,7 @@ static struct exynos_pmu_conf exynos4210_pmu_config[] = { { PMU_TABLE_END,}, }; -static struct exynos_pmu_conf exynos4x12_pmu_config[] = { +static const struct exynos_pmu_conf exynos4x12_pmu_config[] = { { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, @@ -203,7 +204,7 @@ static struct exynos_pmu_conf exynos4x12_pmu_config[] = { { PMU_TABLE_END,}, }; -static struct exynos_pmu_conf exynos4412_pmu_config[] = { +static const struct exynos_pmu_conf exynos4412_pmu_config[] = { { S5P_ARM_CORE2_LOWPWR, { 0x0, 0x0, 0x2 } }, { S5P_DIS_IRQ_CORE2, { 0x0, 0x0, 0x0 } }, { S5P_DIS_IRQ_CENTRAL2, { 0x0, 0x0, 0x0 } }, @@ -213,7 +214,7 @@ static struct exynos_pmu_conf exynos4412_pmu_config[] = { { PMU_TABLE_END,}, }; -static struct exynos_pmu_conf exynos5250_pmu_config[] = { +static const struct exynos_pmu_conf exynos5250_pmu_config[] = { /* { .reg = address, .val = { AFTR, LPA, SLEEP } */ { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, @@ -317,7 +318,7 @@ static struct exynos_pmu_conf exynos5250_pmu_config[] = { { PMU_TABLE_END,}, }; -static void __iomem *exynos5_list_both_cnt_feed[] = { +static void __iomem * const exynos5_list_both_cnt_feed[] = { EXYNOS5_ARM_CORE0_OPTION, EXYNOS5_ARM_CORE1_OPTION, EXYNOS5_ARM_COMMON_OPTION, @@ -331,7 +332,7 @@ static void __iomem *exynos5_list_both_cnt_feed[] = { EXYNOS5_TOP_PWR_SYSMEM_OPTION, }; -static void __iomem *exynos5_list_diable_wfi_wfe[] = { +static void __iomem * const exynos5_list_diable_wfi_wfe[] = { EXYNOS5_ARM_CORE1_OPTION, EXYNOS5_FSYS_ARM_OPTION, EXYNOS5_ISP_ARM_OPTION, diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h index 2cdb63e8ce5c..7c029ce27711 100644 --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h +++ b/arch/arm/mach-exynos/regs-pmu.h @@ -24,31 +24,16 @@ #define S5P_CENTRAL_SEQ_OPTION S5P_PMUREG(0x0208) #define S5P_USE_STANDBY_WFI0 (1 << 16) -#define S5P_USE_STANDBY_WFI1 (1 << 17) -#define S5P_USE_STANDBYWFI_ISP_ARM (1 << 18) #define S5P_USE_STANDBY_WFE0 (1 << 24) -#define S5P_USE_STANDBY_WFE1 (1 << 25) -#define S5P_USE_STANDBYWFE_ISP_ARM (1 << 26) #define S5P_SWRESET S5P_PMUREG(0x0400) #define EXYNOS_SWRESET S5P_PMUREG(0x0400) #define EXYNOS5440_SWRESET S5P_PMUREG(0x00C4) #define S5P_WAKEUP_STAT S5P_PMUREG(0x0600) -#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604) -#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608) - -#define S5P_HDMI_PHY_CONTROL S5P_PMUREG(0x0700) -#define S5P_HDMI_PHY_ENABLE (1 << 0) - -#define S5P_DAC_PHY_CONTROL S5P_PMUREG(0x070C) -#define S5P_DAC_PHY_ENABLE (1 << 0) #define S5P_INFORM0 S5P_PMUREG(0x0800) #define S5P_INFORM1 S5P_PMUREG(0x0804) -#define S5P_INFORM2 S5P_PMUREG(0x0808) -#define S5P_INFORM3 S5P_PMUREG(0x080C) -#define S5P_INFORM4 S5P_PMUREG(0x0810) #define S5P_INFORM5 S5P_PMUREG(0x0814) #define S5P_INFORM6 S5P_PMUREG(0x0818) #define S5P_INFORM7 S5P_PMUREG(0x081C) @@ -119,23 +104,8 @@ #define S5P_GPS_LOWPWR S5P_PMUREG(0x139C) #define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0) -#define S5P_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000) -#define S5P_ARM_CORE0_OPTION S5P_PMUREG(0x2008) #define S5P_ARM_CORE1_CONFIGURATION S5P_PMUREG(0x2080) #define S5P_ARM_CORE1_STATUS S5P_PMUREG(0x2084) -#define S5P_ARM_CORE1_OPTION S5P_PMUREG(0x2088) - -#define S5P_ARM_COMMON_OPTION S5P_PMUREG(0x2408) -#define S5P_TOP_PWR_OPTION S5P_PMUREG(0x2C48) -#define S5P_CAM_OPTION S5P_PMUREG(0x3C08) -#define S5P_TV_OPTION S5P_PMUREG(0x3C28) -#define S5P_MFC_OPTION S5P_PMUREG(0x3C48) -#define S5P_G3D_OPTION S5P_PMUREG(0x3C68) -#define S5P_LCD0_OPTION S5P_PMUREG(0x3C88) -#define S5P_LCD1_OPTION S5P_PMUREG(0x3CA8) -#define S5P_MAUDIO_OPTION S5P_PMUREG(0x3CC8) -#define S5P_GPS_OPTION S5P_PMUREG(0x3CE8) -#define S5P_GPS_ALIVE_OPTION S5P_PMUREG(0x3D08) #define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028) #define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108) @@ -145,28 +115,12 @@ #define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188) #define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8) -#define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00) -#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20) -#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40) -#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60) -#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80) -#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0) - -#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1 #define S5P_CORE_LOCAL_PWR_EN 0x3 #define S5P_INT_LOCAL_PWR_EN 0x7 #define S5P_CHECK_SLEEP 0x00000BAD /* Only for EXYNOS4210 */ -#define S5P_USBDEVICE_PHY_CONTROL S5P_PMUREG(0x0704) -#define S5P_USBDEVICE_PHY_ENABLE (1 << 0) - -#define S5P_USBHOST_PHY_CONTROL S5P_PMUREG(0x0708) -#define S5P_USBHOST_PHY_ENABLE (1 << 0) - -#define S5P_PMU_SATA_PHY_CONTROL S5P_PMUREG(0x0720) - #define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154) #define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174) #define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4) @@ -174,8 +128,6 @@ #define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4) #define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394) -#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0) - /* Only for EXYNOS4x12 */ #define S5P_ISP_ARM_LOWPWR S5P_PMUREG(0x1050) #define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR S5P_PMUREG(0x1054) @@ -343,13 +295,9 @@ #define EXYNOS5_TOP_PWR_OPTION S5P_PMUREG(0x2C48) #define EXYNOS5_TOP_PWR_SYSMEM_OPTION S5P_PMUREG(0x2CC8) #define EXYNOS5_JPEG_MEM_OPTION S5P_PMUREG(0x2F48) -#define EXYNOS5_GSCL_STATUS S5P_PMUREG(0x4004) -#define EXYNOS5_ISP_STATUS S5P_PMUREG(0x4024) #define EXYNOS5_GSCL_OPTION S5P_PMUREG(0x4008) #define EXYNOS5_ISP_OPTION S5P_PMUREG(0x4028) #define EXYNOS5_MFC_OPTION S5P_PMUREG(0x4048) -#define EXYNOS5_G3D_CONFIGURATION S5P_PMUREG(0x4060) -#define EXYNOS5_G3D_STATUS S5P_PMUREG(0x4064) #define EXYNOS5_G3D_OPTION S5P_PMUREG(0x4068) #define EXYNOS5_DISP1_OPTION S5P_PMUREG(0x40A8) #define EXYNOS5_MAU_OPTION S5P_PMUREG(0x40C8) @@ -357,7 +305,6 @@ #define EXYNOS5_USE_SC_FEEDBACK (1 << 1) #define EXYNOS5_USE_SC_COUNTER (1 << 0) -#define EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL (1 << 2) #define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7) #define EXYNOS5_OPTION_USE_STANDBYWFE (1 << 24) diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c index 1f24c1fdfea4..5b57c17c06bd 100644 --- a/arch/arm/mach-imx/platsmp.c +++ b/arch/arm/mach-imx/platsmp.c @@ -92,8 +92,7 @@ static void __init imx_smp_prepare_cpus(unsigned int max_cpus) * secondary cores when booting them. */ asm("mrc p15, 0, %0, c15, c0, 1" : "=r" (g_diag_reg) : : "cc"); - __cpuc_flush_dcache_area(&g_diag_reg, sizeof(g_diag_reg)); - outer_clean_range(__pa(&g_diag_reg), __pa(&g_diag_reg + 1)); + sync_cache_w(&g_diag_reg); } struct smp_operations imx_smp_ops __initdata = { diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c index 9caa4fe95913..78188159484d 100644 --- a/arch/arm/mach-kirkwood/board-dt.c +++ b/arch/arm/mach-kirkwood/board-dt.c @@ -10,55 +10,21 @@ * warranty of any kind, whether express or implied. */ +#include <linux/clk.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_net.h> #include <linux/of_platform.h> -#include <linux/clk-provider.h> #include <linux/dma-mapping.h> #include <linux/irqchip.h> #include <linux/kexec.h> #include <asm/mach/arch.h> -#include <asm/mach/map.h> #include <mach/bridge-regs.h> -#include <linux/platform_data/usb-ehci-orion.h> -#include <plat/irq.h> #include <plat/common.h> #include "common.h" -/* - * There are still devices that doesn't know about DT yet. Get clock - * gates here and add a clock lookup alias, so that old platform - * devices still work. -*/ - -static void __init kirkwood_legacy_clk_init(void) -{ - - struct device_node *np = of_find_compatible_node( - NULL, NULL, "marvell,kirkwood-gating-clock"); - struct of_phandle_args clkspec; - struct clk *clk; - - clkspec.np = np; - clkspec.args_count = 1; - - /* - * The ethernet interfaces forget the MAC address assigned by - * u-boot if the clocks are turned off. Until proper DT support - * is available we always enable them for now. - */ - clkspec.args[0] = CGC_BIT_GE0; - clk = of_clk_get_from_provider(&clkspec); - clk_prepare_enable(clk); - - clkspec.args[0] = CGC_BIT_GE1; - clk = of_clk_get_from_provider(&clkspec); - clk_prepare_enable(clk); -} - #define MV643XX_ETH_MAC_ADDR_LOW 0x0414 #define MV643XX_ETH_MAC_ADDR_HIGH 0x0418 @@ -140,7 +106,7 @@ eth_fixup_skip: static void __init kirkwood_dt_init(void) { - pr_info("Kirkwood: %s, TCLK=%d.\n", kirkwood_id(), kirkwood_tclk); + pr_info("Kirkwood: %s.\n", kirkwood_id()); /* * Disable propagation of mbus errors to the CPU local bus, @@ -156,8 +122,6 @@ static void __init kirkwood_dt_init(void) kirkwood_cpufreq_init(); kirkwood_cpuidle_init(); - /* Setup clocks for legacy devices */ - kirkwood_legacy_clk_init(); kirkwood_pm_init(); kirkwood_dt_eth_fixup(); diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig index ebdda8346a26..ebdba87b9671 100644 --- a/arch/arm/mach-mmp/Kconfig +++ b/arch/arm/mach-mmp/Kconfig @@ -136,4 +136,7 @@ config USB_EHCI_MV_U2O help Enables support for OTG controller which can be switched to host mode. +config MMP_SRAM + bool + endif diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile index 9b702a1dc7b0..98f0f6388e44 100644 --- a/arch/arm/mach-mmp/Makefile +++ b/arch/arm/mach-mmp/Makefile @@ -7,7 +7,8 @@ obj-y += common.o devices.o time.o # SoC support obj-$(CONFIG_CPU_PXA168) += pxa168.o obj-$(CONFIG_CPU_PXA910) += pxa910.o -obj-$(CONFIG_CPU_MMP2) += mmp2.o sram.o +obj-$(CONFIG_CPU_MMP2) += mmp2.o +obj-$(CONFIG_MMP_SRAM) += sram.o ifeq ($(CONFIG_COMMON_CLK), ) obj-y += clock.o diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c index 3f06edcdd0ce..f10a1f58fde9 100644 --- a/arch/arm/mach-msm/platsmp.c +++ b/arch/arm/mach-msm/platsmp.c @@ -99,8 +99,7 @@ static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle) * "cpu" is Linux's internal ID. */ pen_release = cpu_logical_map(cpu); - __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); - outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); + sync_cache_w(&pen_release); /* * Send the secondary CPU a soft interrupt, thereby causing diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h index c612b2c4ed6c..237c86b83390 100644 --- a/arch/arm/mach-mvebu/armada-370-xp.h +++ b/arch/arm/mach-mvebu/armada-370-xp.h @@ -18,8 +18,12 @@ #ifdef CONFIG_SMP #include <linux/cpumask.h> +#define ARMADA_XP_MAX_CPUS 4 + void armada_mpic_send_doorbell(const struct cpumask *mask, unsigned int irq); void armada_xp_mpic_smp_cpu_init(void); +void armada_xp_secondary_startup(void); +extern struct smp_operations armada_xp_smp_ops; #endif #endif /* __MACH_ARMADA_370_XP_H */ diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c index 58adf2fd9cfc..4e9d58148ca7 100644 --- a/arch/arm/mach-mvebu/coherency.c +++ b/arch/arm/mach-mvebu/coherency.c @@ -27,6 +27,7 @@ #include <asm/smp_plat.h> #include <asm/cacheflush.h> #include "armada-370-xp.h" +#include "coherency.h" unsigned long coherency_phys_base; static void __iomem *coherency_base; diff --git a/arch/arm/mach-mvebu/coherency.h b/arch/arm/mach-mvebu/coherency.h index df33ad8a6c08..760226c41353 100644 --- a/arch/arm/mach-mvebu/coherency.h +++ b/arch/arm/mach-mvebu/coherency.h @@ -14,7 +14,9 @@ #ifndef __MACH_370_XP_COHERENCY_H #define __MACH_370_XP_COHERENCY_H -int set_cpu_coherent(int cpu_id, int smp_group_id); +extern unsigned long coherency_phys_base; + +int set_cpu_coherent(unsigned int cpu_id, int smp_group_id); int coherency_init(void); #endif /* __MACH_370_XP_COHERENCY_H */ diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h index e366010e1d91..55449c487c9e 100644 --- a/arch/arm/mach-mvebu/common.h +++ b/arch/arm/mach-mvebu/common.h @@ -15,18 +15,10 @@ #ifndef __ARCH_MVEBU_COMMON_H #define __ARCH_MVEBU_COMMON_H -#define ARMADA_XP_MAX_CPUS 4 - #include <linux/reboot.h> void mvebu_restart(enum reboot_mode mode, const char *cmd); -void armada_370_xp_init_irq(void); -void armada_370_xp_handle_irq(struct pt_regs *regs); - void armada_xp_cpu_die(unsigned int cpu); -int armada_370_xp_coherency_init(void); -int armada_370_xp_pmsu_init(void); -void armada_xp_secondary_startup(void); -extern struct smp_operations armada_xp_smp_ops; + #endif diff --git a/arch/arm/mach-mvebu/hotplug.c b/arch/arm/mach-mvebu/hotplug.c index b228b6a80c85..d95e91047168 100644 --- a/arch/arm/mach-mvebu/hotplug.c +++ b/arch/arm/mach-mvebu/hotplug.c @@ -15,6 +15,7 @@ #include <linux/errno.h> #include <linux/smp.h> #include <asm/proc-fns.h> +#include "common.h" /* * platform-specific code to shutdown a CPU diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c index ff69c2df298b..a6da03f5b24e 100644 --- a/arch/arm/mach-mvebu/platsmp.c +++ b/arch/arm/mach-mvebu/platsmp.c @@ -46,7 +46,7 @@ static struct clk *__init get_cpu_clk(int cpu) return cpu_clk; } -void __init set_secondary_cpus_clock(void) +static void __init set_secondary_cpus_clock(void) { int thiscpu, cpu; unsigned long rate; @@ -94,7 +94,7 @@ static void __init armada_xp_smp_init_cpus(void) set_smp_cross_call(armada_mpic_send_doorbell); } -void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus) +static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus) { struct device_node *node; struct resource res; diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c index 27fc4f049474..d71ef53107c4 100644 --- a/arch/arm/mach-mvebu/pmsu.c +++ b/arch/arm/mach-mvebu/pmsu.c @@ -22,6 +22,7 @@ #include <linux/io.h> #include <linux/smp.h> #include <asm/smp_plat.h> +#include "pmsu.h" static void __iomem *pmsu_mp_base; static void __iomem *pmsu_reset_base; @@ -58,7 +59,7 @@ int armada_xp_boot_cpu(unsigned int cpu_id, void *boot_addr) } #endif -int __init armada_370_xp_pmsu_init(void) +static int __init armada_370_xp_pmsu_init(void) { struct device_node *np; diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c index 5175083cdb34..a7fb89a5b5d9 100644 --- a/arch/arm/mach-mvebu/system-controller.c +++ b/arch/arm/mach-mvebu/system-controller.c @@ -27,6 +27,7 @@ #include <linux/of_address.h> #include <linux/io.h> #include <linux/reboot.h> +#include "common.h" static void __iomem *system_controller_base; @@ -39,14 +40,14 @@ struct mvebu_system_controller { }; static struct mvebu_system_controller *mvebu_sc; -const struct mvebu_system_controller armada_370_xp_system_controller = { +static const struct mvebu_system_controller armada_370_xp_system_controller = { .rstoutn_mask_offset = 0x60, .system_soft_reset_offset = 0x64, .rstoutn_mask_reset_out_en = 0x1, .system_soft_reset = 0x1, }; -const struct mvebu_system_controller orion_system_controller = { +static const struct mvebu_system_controller orion_system_controller = { .rstoutn_mask_offset = 0x108, .system_soft_reset_offset = 0x10c, .rstoutn_mask_reset_out_en = 0x4, diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c index b91002ca92f3..c134a826070a 100644 --- a/arch/arm/mach-orion5x/board-dt.c +++ b/arch/arm/mach-orion5x/board-dt.c @@ -21,7 +21,7 @@ #include <plat/irq.h> #include "common.h" -struct of_dev_auxdata orion5x_auxdata_lookup[] __initdata = { +static struct of_dev_auxdata orion5x_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("marvell,orion-spi", 0xf1010600, "orion_spi.0", NULL), OF_DEV_AUXDATA("marvell,mv64xxx-i2c", 0xf1011000, "mv64xxx_i2c.0", NULL), diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c index 91a5852b44f3..3f1de1111e0f 100644 --- a/arch/arm/mach-orion5x/common.c +++ b/arch/arm/mach-orion5x/common.c @@ -24,7 +24,6 @@ #include <asm/page.h> #include <asm/setup.h> #include <asm/system_misc.h> -#include <asm/timex.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> #include <asm/mach/time.h> @@ -135,7 +134,7 @@ void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) /***************************************************************************** * SPI ****************************************************************************/ -void __init orion5x_spi_init() +void __init orion5x_spi_init(void) { orion_spi_init(SPI_PHYS_BASE); } @@ -185,7 +184,7 @@ static void __init orion5x_crypto_init(void) /***************************************************************************** * Watchdog ****************************************************************************/ -void __init orion5x_wdt_init(void) +static void __init orion5x_wdt_init(void) { orion_wdt_init(); } @@ -246,7 +245,7 @@ void orion5x_setup_wins(void) int orion5x_tclk; -int __init orion5x_find_tclk(void) +static int __init orion5x_find_tclk(void) { u32 dev, rev; diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c index 4b2aefd1d961..dc01c4ffc9a8 100644 --- a/arch/arm/mach-orion5x/db88f5281-setup.c +++ b/arch/arm/mach-orion5x/db88f5281-setup.c @@ -202,7 +202,7 @@ __initcall(db88f5281_7seg_init); * PCI ****************************************************************************/ -void __init db88f5281_pci_preinit(void) +static void __init db88f5281_pci_preinit(void) { int pin; diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c index 30a192b9c517..9654b0cc5892 100644 --- a/arch/arm/mach-orion5x/irq.c +++ b/arch/arm/mach-orion5x/irq.c @@ -16,6 +16,7 @@ #include <mach/bridge-regs.h> #include <plat/orion-gpio.h> #include <plat/irq.h> +#include "common.h" static int __initdata gpio0_irqs[4] = { IRQ_ORION5X_GPIO_0_7, diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c index 7fab67053030..87a12d6930ff 100644 --- a/arch/arm/mach-orion5x/pci.c +++ b/arch/arm/mach-orion5x/pci.c @@ -240,11 +240,11 @@ static int __init pcie_setup(struct pci_sys_data *sys) #define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \ ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ - ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0) + ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : NULL) #define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \ ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ - ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0) + ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : NULL) #define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c) #define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c) diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c index b1cf68493ffc..b576ef5f18a1 100644 --- a/arch/arm/mach-orion5x/rd88f5182-setup.c +++ b/arch/arm/mach-orion5x/rd88f5182-setup.c @@ -108,7 +108,7 @@ static struct platform_device rd88f5182_gpio_leds = { * PCI ****************************************************************************/ -void __init rd88f5182_pci_preinit(void) +static void __init rd88f5182_pci_preinit(void) { int pin; diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c index 7e9064844698..6208d125c1b9 100644 --- a/arch/arm/mach-orion5x/terastation_pro2-setup.c +++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c @@ -77,7 +77,7 @@ static struct platform_device tsp2_nor_flash = { #define TSP2_PCI_SLOT0_OFFS 7 #define TSP2_PCI_SLOT0_IRQ_PIN 11 -void __init tsp2_pci_preinit(void) +static void __init tsp2_pci_preinit(void) { int pin; diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c index e90c0618fdad..9136797addb2 100644 --- a/arch/arm/mach-orion5x/ts209-setup.c +++ b/arch/arm/mach-orion5x/ts209-setup.c @@ -106,7 +106,7 @@ static struct platform_device qnap_ts209_nor_flash = { #define QNAP_TS209_PCI_SLOT0_IRQ_PIN 6 #define QNAP_TS209_PCI_SLOT1_IRQ_PIN 7 -void __init qnap_ts209_pci_preinit(void) +static void __init qnap_ts209_pci_preinit(void) { int pin; diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c index e960855d32ac..db16dae441e2 100644 --- a/arch/arm/mach-orion5x/ts78xx-setup.c +++ b/arch/arm/mach-orion5x/ts78xx-setup.c @@ -57,7 +57,7 @@ static struct map_desc ts78xx_io_desc[] __initdata = { }, }; -void __init ts78xx_map_io(void) +static void __init ts78xx_map_io(void) { orion5x_map_io(); iotable_init(ts78xx_io_desc, ARRAY_SIZE(ts78xx_io_desc)); diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c index 3dbcb1ab6e37..e358b0736dea 100644 --- a/arch/arm/mach-prima2/platsmp.c +++ b/arch/arm/mach-prima2/platsmp.c @@ -106,8 +106,7 @@ static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle) * "cpu" is Linux's internal ID. */ pen_release = cpu_logical_map(cpu); - __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); - outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); + sync_cache_w(&pen_release); /* * Send the secondary CPU SEV, thereby causing the boot monitor to read diff --git a/arch/arm/mach-pxa/am200epd.c b/arch/arm/mach-pxa/am200epd.c index ffa6d811aad8..12fb0f4ae359 100644 --- a/arch/arm/mach-pxa/am200epd.c +++ b/arch/arm/mach-pxa/am200epd.c @@ -293,8 +293,7 @@ static int am200_setup_irq(struct fb_info *info) int ret; ret = request_irq(PXA_GPIO_TO_IRQ(RDY_GPIO_PIN), am200_handle_irq, - IRQF_DISABLED|IRQF_TRIGGER_FALLING, - "AM200", info->par); + IRQF_TRIGGER_FALLING, "AM200", info->par); if (ret) dev_err(&am200_device->dev, "request_irq failed: %d\n", ret); diff --git a/arch/arm/mach-pxa/am300epd.c b/arch/arm/mach-pxa/am300epd.c index 3dfec1ec462d..c9f309ae88c5 100644 --- a/arch/arm/mach-pxa/am300epd.c +++ b/arch/arm/mach-pxa/am300epd.c @@ -241,8 +241,7 @@ static int am300_setup_irq(struct fb_info *info) struct broadsheetfb_par *par = info->par; ret = request_irq(PXA_GPIO_TO_IRQ(RDY_GPIO_PIN), am300_handle_irq, - IRQF_DISABLED|IRQF_TRIGGER_RISING, - "AM300", par); + IRQF_TRIGGER_RISING, "AM300", par); if (ret) dev_err(&am300_device->dev, "request_irq failed: %d\n", ret); diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c index 8eb4e23c561d..6915a9f6b3a3 100644 --- a/arch/arm/mach-pxa/em-x270.c +++ b/arch/arm/mach-pxa/em-x270.c @@ -564,8 +564,7 @@ static int em_x270_mci_init(struct device *dev, } err = request_irq(gpio_to_irq(mmc_cd), em_x270_detect_int, - IRQF_DISABLED | IRQF_TRIGGER_RISING | - IRQF_TRIGGER_FALLING, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "MMC card detect", data); if (err) { dev_err(dev, "can't request MMC card detect IRQ: %d\n", err); diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index b6cc1816463e..0eecd83c624e 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c @@ -235,8 +235,6 @@ static const struct of_device_id intc_ids[] __initconst = { void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int)) { struct device_node *node; - const struct of_device_id *of_id; - struct pxa_intc_conf *conf; struct resource res; int n, ret; @@ -245,8 +243,6 @@ void __init pxa_dt_irq_init(int (*fn)(struct irq_data *, unsigned int)) pr_err("Failed to find interrupt controller in arch-pxa\n"); return; } - of_id = of_match_node(intc_ids, node); - conf = of_id->data; ret = of_property_read_u32(node, "marvell,intc-nr-irqs", &pxa_internal_irq_nr); diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c index fab30d666cc7..a9761c293028 100644 --- a/arch/arm/mach-pxa/magician.c +++ b/arch/arm/mach-pxa/magician.c @@ -634,7 +634,7 @@ static struct platform_device bq24022 = { static int magician_mci_init(struct device *dev, irq_handler_t detect_irq, void *data) { - return request_irq(IRQ_MAGICIAN_SD, detect_irq, IRQF_DISABLED, + return request_irq(IRQ_MAGICIAN_SD, detect_irq, 0, "mmc card detect", data); } diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c index 08ccc0718f31..78b84c0dfc79 100644 --- a/arch/arm/mach-pxa/mainstone.c +++ b/arch/arm/mach-pxa/mainstone.c @@ -401,7 +401,7 @@ static int mainstone_mci_init(struct device *dev, irq_handler_t mstone_detect_in */ MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL; - err = request_irq(MAINSTONE_MMC_IRQ, mstone_detect_int, IRQF_DISABLED, + err = request_irq(MAINSTONE_MMC_IRQ, mstone_detect_int, 0, "MMC card detect", data); if (err) printk(KERN_ERR "mainstone_mci_init: MMC/SD: can't request MMC card detect IRQ\n"); diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c index 9a4e470f162b..2897da2a5df6 100644 --- a/arch/arm/mach-pxa/pcm990-baseboard.c +++ b/arch/arm/mach-pxa/pcm990-baseboard.c @@ -327,7 +327,7 @@ static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int, { int err; - err = request_irq(PCM027_MMCDET_IRQ, mci_detect_int, IRQF_DISABLED, + err = request_irq(PCM027_MMCDET_IRQ, mci_detect_int, 0, "MMC card detect", data); if (err) printk(KERN_ERR "pcm990_mci_init: MMC/SD: can't request MMC " diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c index 0a36d3585f26..051a6555cbf9 100644 --- a/arch/arm/mach-pxa/sharpsl_pm.c +++ b/arch/arm/mach-pxa/sharpsl_pm.c @@ -860,18 +860,18 @@ static int sharpsl_pm_probe(struct platform_device *pdev) /* Register interrupt handlers */ irq = gpio_to_irq(sharpsl_pm.machinfo->gpio_acin); - if (request_irq(irq, sharpsl_ac_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "AC Input Detect", sharpsl_ac_isr)) { + if (request_irq(irq, sharpsl_ac_isr, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "AC Input Detect", sharpsl_ac_isr)) { dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", irq); } irq = gpio_to_irq(sharpsl_pm.machinfo->gpio_batlock); - if (request_irq(irq, sharpsl_fatal_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING, "Battery Cover", sharpsl_fatal_isr)) { + if (request_irq(irq, sharpsl_fatal_isr, IRQF_TRIGGER_FALLING, "Battery Cover", sharpsl_fatal_isr)) { dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", irq); } if (sharpsl_pm.machinfo->gpio_fatal) { irq = gpio_to_irq(sharpsl_pm.machinfo->gpio_fatal); - if (request_irq(irq, sharpsl_fatal_isr, IRQF_DISABLED | IRQF_TRIGGER_FALLING, "Fatal Battery", sharpsl_fatal_isr)) { + if (request_irq(irq, sharpsl_fatal_isr, IRQF_TRIGGER_FALLING, "Fatal Battery", sharpsl_fatal_isr)) { dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", irq); } } @@ -879,7 +879,7 @@ static int sharpsl_pm_probe(struct platform_device *pdev) if (sharpsl_pm.machinfo->batfull_irq) { /* Register interrupt handler. */ irq = gpio_to_irq(sharpsl_pm.machinfo->gpio_batfull); - if (request_irq(irq, sharpsl_chrg_full_isr, IRQF_DISABLED | IRQF_TRIGGER_RISING, "CO", sharpsl_chrg_full_isr)) { + if (request_irq(irq, sharpsl_chrg_full_isr, IRQF_TRIGGER_RISING, "CO", sharpsl_chrg_full_isr)) { dev_err(sharpsl_pm.dev, "Could not get irq %d.\n", irq); } } diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c index 9aa852a8fab9..5fdc9c4f05be 100644 --- a/arch/arm/mach-pxa/time.c +++ b/arch/arm/mach-pxa/time.c @@ -137,7 +137,7 @@ static struct clock_event_device ckevt_pxa_osmr0 = { static struct irqaction pxa_ost0_irq = { .name = "ost0", - .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .flags = IRQF_TIMER | IRQF_IRQPOLL, .handler = pxa_ost0_interrupt, .dev_id = &ckevt_pxa_osmr0, }; diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c index c58043462acd..872dcb20e757 100644 --- a/arch/arm/mach-pxa/trizeps4.c +++ b/arch/arm/mach-pxa/trizeps4.c @@ -332,8 +332,7 @@ static int trizeps4_mci_init(struct device *dev, irq_handler_t mci_detect_int, int err; err = request_irq(TRIZEPS4_MMC_IRQ, mci_detect_int, - IRQF_DISABLED | IRQF_TRIGGER_RISING, - "MMC card detect", data); + IRQF_TRIGGER_RISING, "MMC card detect", data); if (err) { printk(KERN_ERR "trizeps4_mci_init: MMC/SD: can't request" "MMC card detect IRQ\n"); diff --git a/arch/arm/mach-s3c24xx/dma.c b/arch/arm/mach-s3c24xx/dma.c index 4a65cba3295d..a8dafc174fe3 100644 --- a/arch/arm/mach-s3c24xx/dma.c +++ b/arch/arm/mach-s3c24xx/dma.c @@ -742,7 +742,7 @@ int s3c2410_dma_request(enum dma_ch channel, chan->irq_claimed = 1; local_irq_restore(flags); - err = request_irq(chan->irq, s3c2410_dma_irq, IRQF_DISABLED, + err = request_irq(chan->irq, s3c2410_dma_irq, 0, client->name, (void *)chan); local_irq_save(flags); diff --git a/arch/arm/mach-s3c24xx/simtec-usb.c b/arch/arm/mach-s3c24xx/simtec-usb.c index 8dea917e954b..b70aa66efebe 100644 --- a/arch/arm/mach-s3c24xx/simtec-usb.c +++ b/arch/arm/mach-s3c24xx/simtec-usb.c @@ -79,8 +79,7 @@ static void usb_simtec_enableoc(struct s3c2410_hcd_info *info, int on) if (on) { ret = request_irq(BAST_IRQ_USBOC, usb_simtec_ocirq, - IRQF_DISABLED | IRQF_TRIGGER_RISING | - IRQF_TRIGGER_FALLING, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "USB Over-current", info); if (ret != 0) { printk(KERN_ERR "failed to request usb oc irq\n"); diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c index 5629df905fcd..6e72bd5c1d0c 100644 --- a/arch/arm/mach-s3c64xx/mach-smartq.c +++ b/arch/arm/mach-s3c64xx/mach-smartq.c @@ -107,7 +107,7 @@ static void smartq_usb_host_enableoc(struct s3c2410_hcd_info *info, int on) if (on) { ret = request_irq(gpio_to_irq(S3C64XX_GPL(10)), - smartq_usb_host_ocirq, IRQF_DISABLED | + smartq_usb_host_ocirq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "USB host overcurrent", info); if (ret != 0) diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c index 0fa068e30a30..fe071a9130b7 100644 --- a/arch/arm/mach-shmobile/board-ape6evm.c +++ b/arch/arm/mach-shmobile/board-ape6evm.c @@ -168,7 +168,7 @@ static const struct sh_mmcif_plat_data mmcif0_pdata __initconst = { }; static const struct resource mmcif0_resources[] __initconst = { - DEFINE_RES_MEM_NAMED(0xee200000, 0x100, "MMCIF0"), + DEFINE_RES_MEM(0xee200000, 0x100), DEFINE_RES_IRQ(gic_spi(169)), }; @@ -179,7 +179,7 @@ static const struct sh_mobile_sdhi_info sdhi0_pdata __initconst = { }; static const struct resource sdhi0_resources[] __initconst = { - DEFINE_RES_MEM_NAMED(0xee100000, 0x100, "SDHI0"), + DEFINE_RES_MEM(0xee100000, 0x100), DEFINE_RES_IRQ(gic_spi(165)), }; @@ -191,7 +191,7 @@ static const struct sh_mobile_sdhi_info sdhi1_pdata __initconst = { }; static const struct resource sdhi1_resources[] __initconst = { - DEFINE_RES_MEM_NAMED(0xee120000, 0x100, "SDHI1"), + DEFINE_RES_MEM(0xee120000, 0x100), DEFINE_RES_IRQ(gic_spi(166)), }; diff --git a/arch/arm/mach-shmobile/board-bockw-reference.c b/arch/arm/mach-shmobile/board-bockw-reference.c index ae88fdad4b3a..1687df9b267f 100644 --- a/arch/arm/mach-shmobile/board-bockw-reference.c +++ b/arch/arm/mach-shmobile/board-bockw-reference.c @@ -19,7 +19,6 @@ */ #include <linux/of_platform.h> -#include <linux/pinctrl/machine.h> #include <mach/common.h> #include <mach/r8a7778.h> #include <asm/mach/arch.h> diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c index 1a1a4a888632..7df9ea0839db 100644 --- a/arch/arm/mach-shmobile/board-lager-reference.c +++ b/arch/arm/mach-shmobile/board-lager-reference.c @@ -20,16 +20,15 @@ #include <linux/init.h> #include <linux/of_platform.h> +#include <mach/rcar-gen2.h> #include <mach/r8a7790.h> #include <asm/mach/arch.h> static void __init lager_add_standard_devices(void) { - /* clocks are setup late during boot in the case of DT */ r8a7790_clock_init(); - r8a7790_add_dt_devices(); - of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } static const char *lager_boards_compat_dt[] __initdata = { diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c index e0406fd37390..d1a8dddecfc8 100644 --- a/arch/arm/mach-shmobile/board-lager.c +++ b/arch/arm/mach-shmobile/board-lager.c @@ -148,7 +148,7 @@ static const struct sh_mmcif_plat_data mmcif1_pdata __initconst = { }; static const struct resource mmcif1_resources[] __initconst = { - DEFINE_RES_MEM_NAMED(0xee220000, 0x80, "MMCIF1"), + DEFINE_RES_MEM(0xee220000, 0x80), DEFINE_RES_IRQ(gic_spi(170)), }; diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c index da1352f5f71b..4f9e3ec42ddc 100644 --- a/arch/arm/mach-shmobile/board-marzen.c +++ b/arch/arm/mach-shmobile/board-marzen.c @@ -29,6 +29,7 @@ #include <linux/leds.h> #include <linux/dma-mapping.h> #include <linux/pinctrl/machine.h> +#include <linux/platform_data/camera-rcar.h> #include <linux/platform_data/gpio-rcar.h> #include <linux/platform_data/rcar-du.h> #include <linux/platform_data/usb-rcar-phy.h> @@ -259,10 +260,30 @@ static struct platform_device leds_device = { }, }; +/* VIN */ static struct rcar_vin_platform_data vin_platform_data __initdata = { .flags = RCAR_VIN_BT656, }; +#define MARZEN_VIN(idx) \ +static struct resource vin##idx##_resources[] __initdata = { \ + DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000), \ + DEFINE_RES_IRQ(gic_iid(0x5f + (idx))), \ +}; \ + \ +static struct platform_device_info vin##idx##_info __initdata = { \ + .parent = &platform_bus, \ + .name = "r8a7779-vin", \ + .id = idx, \ + .res = vin##idx##_resources, \ + .num_res = ARRAY_SIZE(vin##idx##_resources), \ + .dma_mask = DMA_BIT_MASK(32), \ + .data = &vin_platform_data, \ + .size_data = sizeof(vin_platform_data), \ +} +MARZEN_VIN(1); +MARZEN_VIN(3); + #define MARZEN_CAMERA(idx) \ static struct i2c_board_info camera##idx##_info = { \ I2C_BOARD_INFO("adv7180", 0x20 + (idx)), \ @@ -367,8 +388,8 @@ static void __init marzen_init(void) r8a7779_init_irq_extpin(1); /* IRQ1 as individual interrupt */ r8a7779_add_standard_devices(); - r8a7779_add_vin_device(1, &vin_platform_data); - r8a7779_add_vin_device(3, &vin_platform_data); + platform_device_register_full(&vin1_info); + platform_device_register_full(&vin3_info); platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices)); marzen_add_du_device(); } diff --git a/arch/arm/mach-shmobile/clock-r7s72100.c b/arch/arm/mach-shmobile/clock-r7s72100.c index 4aba20ca127e..0814a508fd61 100644 --- a/arch/arm/mach-shmobile/clock-r7s72100.c +++ b/arch/arm/mach-shmobile/clock-r7s72100.c @@ -170,6 +170,9 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), /* MSTP clocks */ + CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP33]), + + /* ICK */ CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP47]), CLKDEV_ICK_ID("sci_fck", "sh-sci.1", &mstp_clks[MSTP46]), CLKDEV_ICK_ID("sci_fck", "sh-sci.2", &mstp_clks[MSTP45]), diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c index a64f965c7da1..fa1b4773677a 100644 --- a/arch/arm/mach-shmobile/clock-r8a7790.c +++ b/arch/arm/mach-shmobile/clock-r8a7790.c @@ -77,7 +77,7 @@ static struct sh_clk_ops followparent_clk_ops = { }; static struct clk main_clk = { - /* .parent will be set r8a73a4_clock_init */ + /* .parent will be set r8a7790_clock_init */ .ops = &followparent_clk_ops, }; diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c index 5390c6bbbc02..28489978b09c 100644 --- a/arch/arm/mach-shmobile/clock-sh7372.c +++ b/arch/arm/mach-shmobile/clock-sh7372.c @@ -504,10 +504,6 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]), CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]), CLKDEV_CON_ID("hdmi_clk", &div6_reparent_clks[DIV6_HDMI]), - CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]), - CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]), - CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]), - CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]), /* MSTP32 clocks */ CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */ @@ -574,6 +570,11 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */ CLKDEV_DEV_ID("sh_cmt.2", &mstp_clks[MSTP400]), /* CMT2 */ + /* ICK */ + CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]), + CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]), + CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]), + CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]), CLKDEV_ICK_ID("hdmi", "sh_mobile_lcdc_fb.1", &div6_reparent_clks[DIV6_HDMI]), CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]), diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index c92c023f0d27..2aeec468cf7c 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c @@ -625,12 +625,6 @@ static struct clk_lookup lookups[] = { CLKDEV_CON_ID("sdhi0_clk", &div6_clks[DIV6_SDHI0]), CLKDEV_CON_ID("sdhi1_clk", &div6_clks[DIV6_SDHI1]), CLKDEV_CON_ID("sdhi2_clk", &div6_clks[DIV6_SDHI2]), - CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]), - CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]), - CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]), - CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]), - CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.0", &dsi0phy_clk), - CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.1", &dsi1phy_clk), /* MSTP32 clocks */ CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* I2C2 */ @@ -680,6 +674,14 @@ static struct clk_lookup lookups[] = { CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */ CLKDEV_DEV_ID("e6828000.i2c", &mstp_clks[MSTP410]), /* I2C4 */ CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */ + + /* ICK */ + CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]), + CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]), + CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]), + CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]), + CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.0", &dsi0phy_clk), + CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.1", &dsi1phy_clk), }; void __init sh73a0_clock_init(void) diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h index 17af34ed89c8..b40e13631f6a 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7779.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h @@ -3,8 +3,6 @@ #include <linux/sh_clk.h> #include <linux/pm_domain.h> -#include <linux/sh_eth.h> -#include <linux/platform_data/camera-rcar.h> /* HPB-DMA slave IDs */ enum { @@ -13,8 +11,6 @@ enum { HPBDMA_SLAVE_SDHI0_RX, }; -struct platform_device; - struct r8a7779_pm_ch { unsigned long chan_offs; unsigned int chan_bit; @@ -40,9 +36,6 @@ extern void r8a7779_earlytimer_init(void); extern void r8a7779_add_early_devices(void); extern void r8a7779_add_standard_devices(void); extern void r8a7779_add_standard_devices_dt(void); -extern void r8a7779_add_ether_device(struct sh_eth_plat_data *pdata); -extern void r8a7779_add_vin_device(int idx, - struct rcar_vin_platform_data *pdata); extern void r8a7779_init_late(void); extern void r8a7779_clock_init(void); extern void r8a7779_pinmux_init(void); diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 13049e9d691c..8f9453152fb9 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c @@ -598,45 +598,6 @@ static struct platform_device ohci1_device = { .resource = ohci1_resources, }; -/* Ether */ -static struct resource ether_resources[] __initdata = { - { - .start = 0xfde00000, - .end = 0xfde003ff, - .flags = IORESOURCE_MEM, - }, { - .start = gic_iid(0xb4), - .flags = IORESOURCE_IRQ, - }, -}; - -#define R8A7779_VIN(idx) \ -static struct resource vin##idx##_resources[] __initdata = { \ - DEFINE_RES_MEM(0xffc50000 + 0x1000 * (idx), 0x1000), \ - DEFINE_RES_IRQ(gic_iid(0x5f + (idx))), \ -}; \ - \ -static struct platform_device_info vin##idx##_info __initdata = { \ - .parent = &platform_bus, \ - .name = "r8a7779-vin", \ - .id = idx, \ - .res = vin##idx##_resources, \ - .num_res = ARRAY_SIZE(vin##idx##_resources), \ - .dma_mask = DMA_BIT_MASK(32), \ -} - -R8A7779_VIN(0); -R8A7779_VIN(1); -R8A7779_VIN(2); -R8A7779_VIN(3); - -static struct platform_device_info *vin_info_table[] __initdata = { - &vin0_info, - &vin1_info, - &vin2_info, - &vin3_info, -}; - /* HPB-DMA */ /* Asynchronous mode register bits */ @@ -825,24 +786,6 @@ void __init r8a7779_add_standard_devices(void) r8a7779_register_hpb_dmae(); } -void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata) -{ - platform_device_register_resndata(&platform_bus, "r8a777x-ether", -1, - ether_resources, - ARRAY_SIZE(ether_resources), - pdata, sizeof(*pdata)); -} - -void __init r8a7779_add_vin_device(int id, struct rcar_vin_platform_data *pdata) -{ - BUG_ON(id < 0 || id > 3); - - vin_info_table[id]->data = pdata; - vin_info_table[id]->size_data = sizeof(*pdata); - - platform_device_register_full(vin_info_table[id]); -} - /* do nothing for !CONFIG_SMP or !CONFIG_HAVE_TWD */ void __init __weak r8a7779_register_twd(void) { } diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c index c47bcebbcb00..3543c3bacb75 100644 --- a/arch/arm/mach-shmobile/setup-r8a7790.c +++ b/arch/arm/mach-shmobile/setup-r8a7790.c @@ -34,6 +34,10 @@ static const struct resource pfc_resources[] __initconst = { DEFINE_RES_MEM(0xe6060000, 0x250), }; +#define r8a7790_register_pfc() \ + platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, \ + ARRAY_SIZE(pfc_resources)) + #define R8A7790_GPIO(idx) \ static const struct resource r8a7790_gpio##idx##_resources[] __initconst = { \ DEFINE_RES_MEM(0xe6050000 + 0x1000 * (idx), 0x50), \ @@ -65,8 +69,7 @@ R8A7790_GPIO(5); void __init r8a7790_pinmux_init(void) { - platform_device_register_simple("pfc-r8a7790", -1, pfc_resources, - ARRAY_SIZE(pfc_resources)); + r8a7790_register_pfc(); r8a7790_register_gpio(0); r8a7790_register_gpio(1); r8a7790_register_gpio(2); diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index 22de17417fd7..65151c48cbd4 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c @@ -273,7 +273,7 @@ static struct sh_timer_config tmu00_platform_data = { }; static struct resource tmu00_resources[] = { - [0] = DEFINE_RES_MEM_NAMED(0xfff60008, 0xc, "TMU00"), + [0] = DEFINE_RES_MEM(0xfff60008, 0xc), [1] = { .start = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */ .flags = IORESOURCE_IRQ, @@ -298,7 +298,7 @@ static struct sh_timer_config tmu01_platform_data = { }; static struct resource tmu01_resources[] = { - [0] = DEFINE_RES_MEM_NAMED(0xfff60014, 0xc, "TMU00"), + [0] = DEFINE_RES_MEM(0xfff60014, 0xc), [1] = { .start = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */ .flags = IORESOURCE_IRQ, @@ -316,7 +316,7 @@ static struct platform_device tmu01_device = { }; static struct resource i2c0_resources[] = { - [0] = DEFINE_RES_MEM_NAMED(0xe6820000, 0x426, "IIC0"), + [0] = DEFINE_RES_MEM(0xe6820000, 0x426), [1] = { .start = gic_spi(167), .end = gic_spi(170), @@ -325,7 +325,7 @@ static struct resource i2c0_resources[] = { }; static struct resource i2c1_resources[] = { - [0] = DEFINE_RES_MEM_NAMED(0xe6822000, 0x426, "IIC1"), + [0] = DEFINE_RES_MEM(0xe6822000, 0x426), [1] = { .start = gic_spi(51), .end = gic_spi(54), @@ -334,7 +334,7 @@ static struct resource i2c1_resources[] = { }; static struct resource i2c2_resources[] = { - [0] = DEFINE_RES_MEM_NAMED(0xe6824000, 0x426, "IIC2"), + [0] = DEFINE_RES_MEM(0xe6824000, 0x426), [1] = { .start = gic_spi(171), .end = gic_spi(174), @@ -343,7 +343,7 @@ static struct resource i2c2_resources[] = { }; static struct resource i2c3_resources[] = { - [0] = DEFINE_RES_MEM_NAMED(0xe6826000, 0x426, "IIC3"), + [0] = DEFINE_RES_MEM(0xe6826000, 0x426), [1] = { .start = gic_spi(183), .end = gic_spi(186), @@ -352,7 +352,7 @@ static struct resource i2c3_resources[] = { }; static struct resource i2c4_resources[] = { - [0] = DEFINE_RES_MEM_NAMED(0xe6828000, 0x426, "IIC4"), + [0] = DEFINE_RES_MEM(0xe6828000, 0x426), [1] = { .start = gic_spi(187), .end = gic_spi(190), @@ -722,7 +722,7 @@ static struct platform_device pmu_device = { /* an IPMMU module for ICB */ static struct resource ipmmu_resources[] = { - DEFINE_RES_MEM_NAMED(0xfe951000, 0x100, "IPMMU"), + DEFINE_RES_MEM(0xfe951000, 0x100), }; static const char * const ipmmu_dev_names[] = { diff --git a/arch/arm/mach-sti/platsmp.c b/arch/arm/mach-sti/platsmp.c index dce50d983a8e..fa2c33ffac04 100644 --- a/arch/arm/mach-sti/platsmp.c +++ b/arch/arm/mach-sti/platsmp.c @@ -31,8 +31,7 @@ static void write_pen_release(int val) { pen_release = val; smp_wmb(); - __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); - outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); + sync_cache_w(&pen_release); } static DEFINE_SPINLOCK(boot_lock); diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 09e740f58b27..15c09294effa 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -14,6 +14,8 @@ config ARCH_TEGRA select MIGHT_HAVE_CACHE_L2X0 select MIGHT_HAVE_PCI select PINCTRL + select ARCH_HAS_RESET_CONTROLLER + select RESET_CONTROLLER select SOC_BUS select SPARSE_IRQ select USB_ARCH_HAS_EHCI if USB_SUPPORT diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c index 85d28e756bb7..f6f5b54ff95e 100644 --- a/arch/arm/mach-tegra/powergate.c +++ b/arch/arm/mach-tegra/powergate.c @@ -25,6 +25,7 @@ #include <linux/export.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/reset.h> #include <linux/seq_file.h> #include <linux/spinlock.h> #include <linux/clk/tegra.h> @@ -144,11 +145,12 @@ int tegra_powergate_remove_clamping(int id) } /* Must be called with clk disabled, and returns with clk enabled */ -int tegra_powergate_sequence_power_up(int id, struct clk *clk) +int tegra_powergate_sequence_power_up(int id, struct clk *clk, + struct reset_control *rst) { int ret; - tegra_periph_reset_assert(clk); + reset_control_assert(rst); ret = tegra_powergate_power_on(id); if (ret) @@ -165,7 +167,7 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk) goto err_clamp; udelay(10); - tegra_periph_reset_deassert(clk); + reset_control_deassert(rst); return 0; diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c index 1f296e796a4f..a44967f3168c 100644 --- a/arch/arm/mach-ux500/platsmp.c +++ b/arch/arm/mach-ux500/platsmp.c @@ -38,8 +38,7 @@ static void write_pen_release(int val) { pen_release = val; smp_wmb(); - __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); - outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); + sync_cache_w(&pen_release); } static void __iomem *scu_base_addr(void) diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c index 9a7bd137c8fd..1db2a5ca9ab8 100644 --- a/arch/arm/mach-zynq/common.c +++ b/arch/arm/mach-zynq/common.c @@ -25,6 +25,8 @@ #include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/of.h> +#include <linux/irqchip.h> +#include <linux/irqchip/arm-gic.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> @@ -39,11 +41,6 @@ void __iomem *zynq_scu_base; -static struct of_device_id zynq_of_bus_ids[] __initdata = { - { .compatible = "simple-bus", }, - {} -}; - static struct platform_device zynq_cpuidle_device = { .name = "cpuidle-zynq", }; @@ -59,7 +56,7 @@ static void __init zynq_init_machine(void) */ l2x0_of_init(0x02060000, 0xF0F0FFFF); - of_platform_bus_probe(NULL, zynq_of_bus_ids, NULL); + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); platform_device_register(&zynq_cpuidle_device); } @@ -97,6 +94,12 @@ static void __init zynq_map_io(void) zynq_scu_map_io(); } +static void __init zynq_irq_init(void) +{ + gic_arch_extn.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND; + irqchip_init(); +} + static void zynq_system_reset(enum reboot_mode mode, const char *cmd) { zynq_slcr_system_reset(); @@ -110,6 +113,7 @@ static const char * const zynq_dt_match[] = { DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform") .smp = smp_ops(zynq_smp_ops), .map_io = zynq_map_io, + .init_irq = zynq_irq_init, .init_machine = zynq_init_machine, .init_time = zynq_timer_init, .dt_compat = zynq_dt_match, diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h index 3040d219570f..c22c92cea8cb 100644 --- a/arch/arm/mach-zynq/common.h +++ b/arch/arm/mach-zynq/common.h @@ -17,6 +17,8 @@ #ifndef __MACH_ZYNQ_COMMON_H__ #define __MACH_ZYNQ_COMMON_H__ +void zynq_secondary_startup(void); + extern int zynq_slcr_init(void); extern void zynq_slcr_system_reset(void); extern void zynq_slcr_cpu_stop(int cpu); diff --git a/arch/arm/mach-zynq/headsmp.S b/arch/arm/mach-zynq/headsmp.S index d4cd5f34fe5c..57a32869f0aa 100644 --- a/arch/arm/mach-zynq/headsmp.S +++ b/arch/arm/mach-zynq/headsmp.S @@ -18,5 +18,9 @@ zynq_secondary_trampoline_jump: .word /* cpu 1 */ .globl zynq_secondary_trampoline_end zynq_secondary_trampoline_end: - ENDPROC(zynq_secondary_trampoline) + +ENTRY(zynq_secondary_startup) + bl v7_invalidate_l1 + b secondary_startup +ENDPROC(zynq_secondary_startup) diff --git a/arch/arm/mach-zynq/platsmp.c b/arch/arm/mach-zynq/platsmp.c index 689fbbc3d9c8..abc82ef085c1 100644 --- a/arch/arm/mach-zynq/platsmp.c +++ b/arch/arm/mach-zynq/platsmp.c @@ -39,11 +39,6 @@ int zynq_cpun_start(u32 address, int cpu) u32 trampoline_code_size = &zynq_secondary_trampoline_end - &zynq_secondary_trampoline; - if (cpu > ncores) { - pr_warn("CPU No. is not available in the system\n"); - return -1; - } - /* MS: Expectation that SLCR are directly map and accessible */ /* Not possible to jump to non aligned address */ if (!(address & 3) && (!address || (address >= trampoline_code_size))) { @@ -95,7 +90,7 @@ EXPORT_SYMBOL(zynq_cpun_start); static int zynq_boot_secondary(unsigned int cpu, struct task_struct *idle) { - return zynq_cpun_start(virt_to_phys(secondary_startup), cpu); + return zynq_cpun_start(virt_to_phys(zynq_secondary_startup), cpu); } /* @@ -114,23 +109,23 @@ static void __init zynq_smp_init_cpus(void) static void __init zynq_smp_prepare_cpus(unsigned int max_cpus) { - int i; - - /* - * Initialise the present map, which describes the set of CPUs - * actually populated at the present time. - */ - for (i = 0; i < max_cpus; i++) - set_cpu_present(i, true); - scu_enable(zynq_scu_base); } +#ifdef CONFIG_HOTPLUG_CPU +static int zynq_cpu_kill(unsigned cpu) +{ + zynq_slcr_cpu_stop(cpu); + return 1; +} +#endif + struct smp_operations zynq_smp_ops __initdata = { .smp_init_cpus = zynq_smp_init_cpus, .smp_prepare_cpus = zynq_smp_prepare_cpus, .smp_boot_secondary = zynq_boot_secondary, #ifdef CONFIG_HOTPLUG_CPU .cpu_die = zynq_platform_cpu_die, + .cpu_kill = zynq_cpu_kill, #endif }; diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c index c66d163d7a2a..830ff07f3385 100644 --- a/arch/arm/plat-orion/common.c +++ b/arch/arm/plat-orion/common.c @@ -22,6 +22,7 @@ #include <linux/platform_data/dma-mv_xor.h> #include <linux/platform_data/usb-ehci-orion.h> #include <mach/bridge-regs.h> +#include <plat/common.h> /* Create a clkdev entry for a given device/clk */ void __init orion_clkdev_add(const char *con_id, const char *dev_id, @@ -256,7 +257,7 @@ static __init void ge_complete( /***************************************************************************** * GE00 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data orion_ge00_shared_data; +static struct mv643xx_eth_shared_platform_data orion_ge00_shared_data; static struct resource orion_ge00_shared_resources[] = { { @@ -322,7 +323,7 @@ void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data, /***************************************************************************** * GE01 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data orion_ge01_shared_data; +static struct mv643xx_eth_shared_platform_data orion_ge01_shared_data; static struct resource orion_ge01_shared_resources[] = { { @@ -373,7 +374,7 @@ void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data, /***************************************************************************** * GE10 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data orion_ge10_shared_data; +static struct mv643xx_eth_shared_platform_data orion_ge10_shared_data; static struct resource orion_ge10_shared_resources[] = { { @@ -422,7 +423,7 @@ void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data, /***************************************************************************** * GE11 ****************************************************************************/ -struct mv643xx_eth_shared_platform_data orion_ge11_shared_data; +static struct mv643xx_eth_shared_platform_data orion_ge11_shared_data; static struct resource orion_ge11_shared_resources[] = { { diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c index 9d2b2ac74938..15921a1839d7 100644 --- a/arch/arm/plat-orion/time.c +++ b/arch/arm/plat-orion/time.c @@ -17,6 +17,7 @@ #include <linux/interrupt.h> #include <linux/irq.h> #include <linux/sched_clock.h> +#include <plat/time.h> /* * MBus bridge block registers. @@ -174,7 +175,7 @@ static irqreturn_t orion_timer_interrupt(int irq, void *dev_id) static struct irqaction orion_timer_irq = { .name = "orion_tick", - .flags = IRQF_DISABLED | IRQF_TIMER, + .flags = IRQF_TIMER, .handler = orion_timer_interrupt }; diff --git a/arch/arm/plat-pxa/dma.c b/arch/arm/plat-pxa/dma.c index 79ef102e3b2b..054fc5a1a11c 100644 --- a/arch/arm/plat-pxa/dma.c +++ b/arch/arm/plat-pxa/dma.c @@ -377,7 +377,7 @@ int __init pxa_init_dma(int irq, int num_ch) spin_lock_init(&dma_channels[i].lock); } - ret = request_irq(irq, dma_irq_handler, IRQF_DISABLED, "DMA", NULL); + ret = request_irq(irq, dma_irq_handler, 0, "DMA", NULL); if (ret) { printk (KERN_CRIT "Wow! Can't register IRQ for DMA\n"); kfree(dma_channels); diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 6d95d60276d6..58645a58d0d8 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig @@ -24,7 +24,6 @@ config PLAT_S5P select S3C_GPIO_TRACK select S5P_GPIO_DRVSTR select SAMSUNG_CLKSRC if !COMMON_CLK - select SAMSUNG_GPIOLIB_4BIT help Base platform code for Samsung's S5P series SoC. @@ -115,13 +114,6 @@ config S5P_GPIO_INT # options for gpio configuration support -config SAMSUNG_GPIOLIB_4BIT - bool - help - GPIOlib file contains the 4 bit modification functions for gpio - configuration. GPIOlib shall be compiled only for S3C64XX and S5P - series of processors. - config S5P_GPIO_DRVSTR bool help diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h index 6bc1a8f471e3..ff6063f0d5ea 100644 --- a/arch/arm/plat-samsung/include/plat/pm.h +++ b/arch/arm/plat-samsung/include/plat/pm.h @@ -101,8 +101,8 @@ struct pm_uart_save { /* helper functions to save/restore lists of registers. */ extern void s3c_pm_do_save(struct sleep_save *ptr, int count); -extern void s3c_pm_do_restore(struct sleep_save *ptr, int count); -extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count); +extern void s3c_pm_do_restore(const struct sleep_save *ptr, int count); +extern void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count); #ifdef CONFIG_SAMSUNG_PM extern int s3c_irq_wake(struct irq_data *data, unsigned int state); diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c index d0c23010b693..e5b0f2c2d884 100644 --- a/arch/arm/plat-samsung/pm.c +++ b/arch/arm/plat-samsung/pm.c @@ -28,8 +28,10 @@ #ifdef CONFIG_SAMSUNG_ATAGS #include <mach/hardware.h> #include <mach/map.h> +#ifndef CONFIG_ARCH_EXYNOS #include <mach/regs-clock.h> #include <mach/regs-irq.h> +#endif #include <mach/irqs.h> #endif @@ -182,7 +184,7 @@ void s3c_pm_do_save(struct sleep_save *ptr, int count) * restore the UARTs state yet */ -void s3c_pm_do_restore(struct sleep_save *ptr, int count) +void s3c_pm_do_restore(const struct sleep_save *ptr, int count) { for (; count > 0; count--, ptr++) { printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n", @@ -203,7 +205,7 @@ void s3c_pm_do_restore(struct sleep_save *ptr, int count) * peripherals, as things may be changing! */ -void s3c_pm_do_restore_core(struct sleep_save *ptr, int count) +void s3c_pm_do_restore_core(const struct sleep_save *ptr, int count) { for (; count > 0; count--, ptr++) __raw_writel(ptr->val, ptr->reg); diff --git a/arch/arm/plat-samsung/s5p-irq-pm.c b/arch/arm/plat-samsung/s5p-irq-pm.c index 7c1e3b7072fc..591498035916 100644 --- a/arch/arm/plat-samsung/s5p-irq-pm.c +++ b/arch/arm/plat-samsung/s5p-irq-pm.c @@ -22,7 +22,10 @@ #include <mach/map.h> #include <mach/regs-gpio.h> + +#ifndef CONFIG_ARCH_EXYNOS #include <mach/regs-irq.h> +#endif /* state for IRQs over sleep */ diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c index 39895d892c3b..53feb90c840c 100644 --- a/arch/arm/plat-versatile/platsmp.c +++ b/arch/arm/plat-versatile/platsmp.c @@ -27,8 +27,7 @@ static void write_pen_release(int val) { pen_release = val; smp_wmb(); - __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release)); - outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1)); + sync_cache_w(&pen_release); } static DEFINE_SPINLOCK(boot_lock); |