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authorThomas Gleixner <tglx@linutronix.de>2016-12-18 15:06:27 +0100
committerThomas Gleixner <tglx@linutronix.de>2016-12-18 16:35:15 +0100
commit16588f659257495212ac6b9beaf008d9b19e8165 (patch)
tree1cc8e696e19a585855fc2fcefc3a2427bd31faf7 /arch
parent5bae156241e05d25171b18ee43e49f103c3f8097 (diff)
x86/tsc: Annotate printouts as firmware bug
Make it more obvious that the BIOS is screwed up. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Roland Scheidegger <rscheidegger_lists@hispeed.ch> Cc: Bruce Schlobohm <bruce.schlobohm@intel.com> Cc: Kevin Stanton <kevin.b.stanton@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Borislav Petkov <bp@alien8.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/kernel/tsc_sync.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/x86/kernel/tsc_sync.c b/arch/x86/kernel/tsc_sync.c
index 9151f0ce6a42..1d8508fd15f7 100644
--- a/arch/x86/kernel/tsc_sync.c
+++ b/arch/x86/kernel/tsc_sync.c
@@ -76,7 +76,8 @@ static void tsc_sanitize_first_cpu(struct tsc_adjust *cur, s64 bootval,
* deadline timer creates an interrupt storm. Sigh!
*/
if ((bootcpu && bootval != 0) || (!bootcpu && bootval < 0)) {
- pr_warn("TSC ADJUST: CPU%u: %lld force to 0\n", cpu, bootval);
+ pr_warn(FW_BUG "TSC ADJUST: CPU%u: %lld force to 0\n", cpu,
+ bootval);
wrmsrl(MSR_IA32_TSC_ADJUST, 0);
bootval = 0;
}
@@ -141,7 +142,7 @@ bool tsc_store_and_check_tsc_adjust(bool bootcpu)
* package.
*/
if (bootval != ref->bootval) {
- pr_warn("TSC ADJUST differs: Reference CPU%u: %lld CPU%u: %lld\n",
+ pr_warn(FW_BUG "TSC ADJUST differs: Reference CPU%u: %lld CPU%u: %lld\n",
refcpu, ref->bootval, cpu, bootval);
}
/*