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authorNicholas Piggin <npiggin@gmail.com>2019-03-07 05:28:31 +0800
committerLey Foon Tan <ley.foon.tan@intel.com>2019-03-07 06:00:48 +0800
commit21e6bff5e0ef0033d776e64c40e6873d7c75e74b (patch)
tree501dd4adec10abc825735b5d44bcdebc8c721cd5 /arch
parent3ac23944de570df7a6309425aeef063be38f37c4 (diff)
nios2: Fix update_mmu_cache preload the TLB with the new PTE
There is a bug in the TLB preload caused by the pid not being shifted to the correct location in tlbmisc register. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Tested-by: Guenter Roeck <linux@roeck-us.net>
Diffstat (limited to 'arch')
-rw-r--r--arch/nios2/mm/tlb.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/nios2/mm/tlb.c b/arch/nios2/mm/tlb.c
index af8711885569..7fea59e53f94 100644
--- a/arch/nios2/mm/tlb.c
+++ b/arch/nios2/mm/tlb.c
@@ -70,7 +70,8 @@ static void replace_tlb_one_pid(unsigned long addr, unsigned long mmu_pid, unsig
if (pid != mmu_pid)
continue;
- tlbmisc = mmu_pid | TLBMISC_WE | (way << TLBMISC_WAY_SHIFT);
+ tlbmisc = (mmu_pid << TLBMISC_PID_SHIFT) | TLBMISC_WE |
+ (way << TLBMISC_WAY_SHIFT);
WRCTL(CTL_TLBMISC, tlbmisc);
if (tlbacc == 0)
WRCTL(CTL_PTEADDR, pteaddr_invalid(addr));