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authorShawn Guo <shawn.guo@linaro.org>2012-08-11 11:17:42 +0800
committerShawn Guo <shawn.guo@linaro.org>2012-09-11 16:26:45 +0800
commit52ccd4920301b9fecbac577ad4283995730ecf76 (patch)
treebe6f8ed912c50d598c09b735dddff1efcc87af17 /arch
parente30ba89fdf3891c3ff32d25a73fbffd37e893572 (diff)
ARM: dts: imx6q: sort iomuxc sub-nodes in name
Sort iomuxc sub-nodes in name so that the node can be located a little bit easier. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi20
1 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index d5ced4614016..5612ccf2a563 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -522,6 +522,16 @@
};
};
+ ecspi1 {
+ pinctrl_ecspi1_1: ecspi1grp-1 {
+ fsl,pins = <
+ 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
+ 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
+ 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
+ >;
+ };
+ };
+
gpmi-nand {
pinctrl_gpmi_nand_1: gpmi-nand-1 {
fsl,pins = <
@@ -599,16 +609,6 @@
>;
};
};
-
- ecspi1 {
- pinctrl_ecspi1_1: ecspi1grp-1 {
- fsl,pins = <
- 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
- 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
- 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
- >;
- };
- };
};
dcic@020e4000 { /* DCIC1 */