diff options
| author | Russell King <rmk+kernel@armlinux.org.uk> | 2016-12-11 16:05:38 +0000 |
|---|---|---|
| committer | Russell King (Oracle) <rmk+kernel@armlinux.org.uk> | 2022-06-21 10:58:10 +0100 |
| commit | 9cec021e8346871bcf2c9b5555550653b9c1bb2f (patch) | |
| tree | 2325afd31e1901679c93a67be2fcd84b820c9556 /arch | |
| parent | 722270b5bcc784fe0a120cae3746796d7044ac32 (diff) | |
arm64: dts: marvell: mcbin: add pinctrls for 10G PHYs
Add the pinctrl settings and interrupts for the 10G PHYs.
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts index 68c27f22ff57..2bf538d7aec6 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts @@ -14,20 +14,47 @@ "marvell,armada-ap806-quad", "marvell,armada-ap806"; }; +&cp0_pinctrl { + cp0_xg_mdio_pins: xg-mdio-pins { + marvell,pins = "mpp42", "mpp43"; + marvell,function = "xg"; + }; + cp0_phy1_pins: phy1-pins { /* phy interrupt */ + marvell,pins = "mpp49"; + marvell,function = "gpio"; + }; + cp0_phy0_pins: phy0-pins { /* phy interrupt */ + marvell,pins = "mpp50"; + marvell,function = "gpio"; + }; +}; + &cp0_xmdio { + pinctrl-names = "default"; + pinctrl-0 = <&cp0_xg_mdio_pins>; status = "okay"; phy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c45"; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_phy0_pins &cp1_phy0_pins>; + /* should use in-band negotiation */ reg = <0>; sfp = <&sfp_eth0>; + interrupt-parent = <&cp0_gpio2>; + interrupts = <18 IRQ_TYPE_LEVEL_LOW>; marvell,led-mode = /bits/ 16 <0x0129 0x095d 0x0855>; }; phy8: ethernet-phy@8 { compatible = "ethernet-phy-ieee802.3-c45"; + pinctrl-names = "default"; + pinctrl-0 = <&cp0_phy1_pins &cp1_phy1_pins>; + /* should use in-band negotiation */ reg = <8>; sfp = <&sfp_eth1>; + interrupt-parent = <&cp0_gpio2>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; marvell,led-mode = /bits/ 16 <0x0129 0x095d 0x0855>; }; }; @@ -45,3 +72,14 @@ phy = <&phy8>; phy-mode = "10gbase-r"; }; + +&cp1_pinctrl { + cp1_phy1_pins: phy1-pins { /* phy reset */ + marvell,pins = "mpp9"; + marvell,function = "gpio"; + }; + cp1_phy0_pins: phy0-pins { /* phy reset */ + marvell,pins = "mpp31"; + marvell,function = "gpio"; + }; +}; |