diff options
| author | Borislav Petkov <bp@suse.de> | 2021-10-15 12:46:25 +0200 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2021-10-16 12:37:50 +0200 |
| commit | b2381acd3fd9bacd2c63f53b2c610c89959b31cc (patch) | |
| tree | 06fa807068753d83013046b19d3a11f0f6450de9 /arch | |
| parent | 711885906b5c2df90746a51f4cd674f1ab9fbb1d (diff) | |
x86/fpu: Mask out the invalid MXCSR bits properly
This is a fix for the fix (yeah, /facepalm).
The correct mask to use is not the negation of the MXCSR_MASK but the
actual mask which contains the supported bits in the MXCSR register.
Reported and debugged by Ville Syrjälä <ville.syrjala@linux.intel.com>
Fixes: d298b03506d3 ("x86/fpu: Restore the masking out of reserved MXCSR bits")
Signed-off-by: Borislav Petkov <bp@suse.de>
Tested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Tested-by: Ser Olmy <ser.olmy@protonmail.com>
Cc: <stable@vger.kernel.org>
Link: https://lore.kernel.org/r/YWgYIYXLriayyezv@intel.com
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86/kernel/fpu/signal.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/kernel/fpu/signal.c b/arch/x86/kernel/fpu/signal.c index fa17a27390ab..831b25c5e705 100644 --- a/arch/x86/kernel/fpu/signal.c +++ b/arch/x86/kernel/fpu/signal.c @@ -385,7 +385,7 @@ static int __fpu_restore_sig(void __user *buf, void __user *buf_fx, return -EINVAL; } else { /* Mask invalid bits out for historical reasons (broken hardware). */ - fpu->state.fxsave.mxcsr &= ~mxcsr_feature_mask; + fpu->state.fxsave.mxcsr &= mxcsr_feature_mask; } /* Enforce XFEATURE_MASK_FPSSE when XSAVE is enabled */ |