diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2023-12-04 12:57:01 +0100 |
|---|---|---|
| committer | Andrew Morton <akpm@linux-foundation.org> | 2023-12-10 17:21:40 -0800 |
| commit | ec47b986e53e5617e9ed1c74fc3db04983a2d782 (patch) | |
| tree | 073d3b92c7bdcbb33f23b4deb17eda7ec65e3492 /arch | |
| parent | e021227afb5867738482c2dc0970191772cd0d4e (diff) | |
mips: fix tlb_init() prototype
There are two definitions for tlb_init(), but no global declaration:
arch/mips/mm/tlb-r4k.c:552:6: error: no previous prototype for 'tlb_init' [-Werror=missing-prototypes]
arch/mips/mm/tlb-r3k.c:244:6: error: no previous prototype for 'tlb_init' [-Werror=missing-prototypes]
Move the declaration to asm/setup.h and included it as needed.
Link: https://lkml.kernel.org/r/20231204115710.2247097-12-arnd@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Stephen Rothwell <sfr@rothwell.id.au>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/include/asm/setup.h | 1 | ||||
| -rw-r--r-- | arch/mips/kernel/traps.c | 2 | ||||
| -rw-r--r-- | arch/mips/mm/tlb-r3k.c | 1 | ||||
| -rw-r--r-- | arch/mips/mm/tlb-r4k.c | 1 |
4 files changed, 3 insertions, 2 deletions
diff --git a/arch/mips/include/asm/setup.h b/arch/mips/include/asm/setup.h index 8c56b862fd9c..4dce41138bad 100644 --- a/arch/mips/include/asm/setup.h +++ b/arch/mips/include/asm/setup.h @@ -27,5 +27,6 @@ extern unsigned long ebase; extern unsigned int hwrena; extern void per_cpu_trap_init(bool); extern void cpu_cache_init(void); +extern void tlb_init(void); #endif /* __SETUP_H */ diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 246c6a6b0261..c58c0c3c5b40 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2157,8 +2157,6 @@ void *set_vi_handler(int n, vi_handler_t addr) return set_vi_srs_handler(n, addr, 0); } -extern void tlb_init(void); - /* * Timer interrupt */ diff --git a/arch/mips/mm/tlb-r3k.c b/arch/mips/mm/tlb-r3k.c index 1fb2cf8c8bfa..f6db65410c65 100644 --- a/arch/mips/mm/tlb-r3k.c +++ b/arch/mips/mm/tlb-r3k.c @@ -23,6 +23,7 @@ #include <asm/io.h> #include <asm/bootinfo.h> #include <asm/cpu.h> +#include <asm/setup.h> #include <asm/tlbex.h> #undef DEBUG_TLB diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index a542b255019a..44411b20c7ec 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -24,6 +24,7 @@ #include <asm/tlb.h> #include <asm/tlbex.h> #include <asm/tlbmisc.h> +#include <asm/setup.h> /* * LOONGSON-2 has a 4 entry itlb which is a subset of jtlb, LOONGSON-3 has |