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| author | Max Filippov <jcmvbkbc@gmail.com> | 2022-04-13 22:44:36 -0700 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2022-04-15 18:44:02 -0700 |
| commit | 839769c35477d4acc2369e45000ca7b0b6af39a7 (patch) | |
| tree | 4404e5546ff147db429f40dc4fc90526e8629d22 /crypto | |
| parent | eb5adc70754d26a260f8b42d39db42da0d0af500 (diff) | |
xtensa: fix a7 clobbering in coprocessor context load/store
Fast coprocessor exception handler saves a3..a6, but coprocessor context
load/store code uses a4..a7 as temporaries, potentially clobbering a7.
'Potentially' because coprocessor state load/store macros may not use
all four temporary registers (and neither FPU nor HiFi macros do).
Use a3..a6 as intended.
Cc: stable@vger.kernel.org
Fixes: c658eac628aa ("[XTENSA] Add support for configurable registers and coprocessors")
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'crypto')
0 files changed, 0 insertions, 0 deletions