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authorTang Yuantian <Yuantian.Tang@nxp.com>2017-01-20 14:59:36 +0800
committerTejun Heo <tj@kernel.org>2017-01-20 08:31:14 -0500
commitce8f45370e118fb6d5fe820b97558b9e2e2fece5 (patch)
tree540c60abaf63548f4b51a88b0c262fe2bd64c060 /drivers/ata
parent01f2901a264d954d3985e8bce1bf637ae52d4918 (diff)
ahci: qoriq: added ls2088a platforms support
Ls2088a is new introduced arm-based soc with sata support with following features: 1. Complies with the serial ATA 3.0 specification and the AHCI 1.3.1 specification 2. Contains a high-speed descriptor-based DMA controller 3. Supports the following: a. Speeds of 1.5 Gb/s (first-generation SATA), 3 Gb/s (second-generation SATA), and 6 Gb/s (third-generation SATA) b. FIS-based switching c. Native command queuing (NCQ) commands d. Port multiplier operation e. Asynchronous notification f. SATA BIST mode Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Tejun Heo <tj@kernel.org>
Diffstat (limited to 'drivers/ata')
-rw-r--r--drivers/ata/ahci_qoriq.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/ata/ahci_qoriq.c b/drivers/ata/ahci_qoriq.c
index 137b1c76f259..85d833289f28 100644
--- a/drivers/ata/ahci_qoriq.c
+++ b/drivers/ata/ahci_qoriq.c
@@ -53,6 +53,7 @@ enum ahci_qoriq_type {
AHCI_LS1043A,
AHCI_LS2080A,
AHCI_LS1046A,
+ AHCI_LS2088A,
};
struct ahci_qoriq_priv {
@@ -67,6 +68,7 @@ static const struct of_device_id ahci_qoriq_of_match[] = {
{ .compatible = "fsl,ls1043a-ahci", .data = (void *)AHCI_LS1043A},
{ .compatible = "fsl,ls2080a-ahci", .data = (void *)AHCI_LS2080A},
{ .compatible = "fsl,ls1046a-ahci", .data = (void *)AHCI_LS1046A},
+ { .compatible = "fsl,ls2088a-ahci", .data = (void *)AHCI_LS2088A},
{},
};
MODULE_DEVICE_TABLE(of, ahci_qoriq_of_match);
@@ -198,6 +200,13 @@ static int ahci_qoriq_phy_init(struct ahci_host_priv *hpriv)
if (qpriv->is_dmacoherent)
writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
break;
+
+ case AHCI_LS2088A:
+ writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1);
+ writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS);
+ if (qpriv->is_dmacoherent)
+ writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC);
+ break;
}
return 0;