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authorAkinobu Mita <akinobu.mita@gmail.com>2017-01-01 03:04:36 +0900
committerStephen Boyd <sboyd@codeaurora.org>2017-01-09 16:38:30 -0800
commit5508124cccb8bd7bebe7552022f7082e37dc6e50 (patch)
tree423e10a0f23d416e1afa50b4816d3b4b2d2b0438 /drivers/clk/Kconfig
parent8e18d065899e57f2065cea2d34249b966c631338 (diff)
clk: cdce925: add support for CDCE913, CDCE937, and CDCE949
The CDCE925 is a member of the CDCE(L)9xx programmable clock generator family. There are also CDCE913, CDCE937, CDCE949 which have different number of PLLs and outputs. The clk-cdce925 driver supports only CDCE925 in the family. This adds support for the CDCE913, CDCE937, CDCE949, too. Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Cc: Mike Looijmans <mike.looijmans@topic.nl> Cc: Michael Turquette <mturquette@linaro.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/Kconfig')
-rw-r--r--drivers/clk/Kconfig11
1 files changed, 6 insertions, 5 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 56c1998ced3e..664abe9e085b 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -95,16 +95,17 @@ config COMMON_CLK_CDCE706
This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
config COMMON_CLK_CDCE925
- tristate "Clock driver for TI CDCE925 devices"
+ tristate "Clock driver for TI CDCE913/925/937/949 devices"
depends on I2C
depends on OF
select REGMAP_I2C
help
---help---
- This driver supports the TI CDCE925 programmable clock synthesizer.
- The chip contains two PLLs with spread-spectrum clocking support and
- five output dividers. The driver only supports the following setup,
- and uses a fixed setting for the output muxes.
+ This driver supports the TI CDCE913/925/937/949 programmable clock
+ synthesizer. Each chip has different number of PLLs and outputs.
+ For example, the CDCE925 contains two PLLs with spread-spectrum
+ clocking support and five output dividers. The driver only supports
+ the following setup, and uses a fixed setting for the output muxes.
Y1 is derived from the input clock
Y2 and Y3 derive from PLL1
Y4 and Y5 derive from PLL2