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authorMauro Carvalho Chehab <mchehab+samsung@kernel.org>2018-11-06 05:11:16 -0500
committerMauro Carvalho Chehab <mchehab+samsung@kernel.org>2018-11-06 05:11:16 -0500
commit215237a5e436f72e8ee5b53243acf88a16e3ac01 (patch)
tree32723b380e1e3aa4a90f1134a29c587da041b0fe /drivers/clk/actions/owl-s700.c
parentdf18bfd35bbf7cb1a420b5beede1de29343793b3 (diff)
parent651022382c7f8da46cb4872a545ee1da6d097d2a (diff)
Merge tag 'v4.20-rc1' into patchwork
Linux 4.20-rc1 * tag 'v4.20-rc1': (836 commits) Linux 4.20-rc1 sched/topology: Fix off by one bug memory_hotplug: cond_resched in __remove_pages bfs: add sanity check at bfs_fill_super() kernel/sysctl.c: remove duplicated include kernel/kexec_file.c: remove some duplicated includes mm, thp: consolidate THP gfp handling into alloc_hugepage_direct_gfpmask ocfs2: fix clusters leak in ocfs2_defrag_extent() ocfs2: dlmglue: clean up timestamp handling ocfs2: don't put and assigning null to bh allocated outside ocfs2: fix a misuse a of brelse after failing ocfs2_check_dir_entry ocfs2: don't use iocb when EIOCBQUEUED returns ocfs2: without quota support, avoid calling quota recovery ocfs2: remove ocfs2_is_o2cb_active() mm: thp: relax __GFP_THISNODE for MADV_HUGEPAGE mappings include/linux/notifier.h: SRCU: fix ctags mm: handle no memcg case in memcg_kmem_charge() properly ARM: dts: stm32: update HASH1 dmas property on stm32mp157c ARM: orion: avoid VLA in orion_mpp_conf iov_iter: Fix 9p virtio breakage ...
Diffstat (limited to 'drivers/clk/actions/owl-s700.c')
-rw-r--r--drivers/clk/actions/owl-s700.c55
1 files changed, 53 insertions, 2 deletions
diff --git a/drivers/clk/actions/owl-s700.c b/drivers/clk/actions/owl-s700.c
index 5e9531392ee5..a2f34d13fb54 100644
--- a/drivers/clk/actions/owl-s700.c
+++ b/drivers/clk/actions/owl-s700.c
@@ -20,8 +20,10 @@
#include "owl-gate.h"
#include "owl-mux.h"
#include "owl-pll.h"
+#include "owl-reset.h"
#include <dt-bindings/clock/actions,s700-cmu.h>
+#include <dt-bindings/reset/actions,s700-reset.h>
#define CMU_COREPLL (0x0000)
#define CMU_DEVPLL (0x0004)
@@ -569,20 +571,69 @@ static struct clk_hw_onecell_data s700_hw_clks = {
.num = CLK_NR_CLKS,
};
-static const struct owl_clk_desc s700_clk_desc = {
+static const struct owl_reset_map s700_resets[] = {
+ [RESET_DE] = { CMU_DEVRST0, BIT(0) },
+ [RESET_LCD0] = { CMU_DEVRST0, BIT(1) },
+ [RESET_DSI] = { CMU_DEVRST0, BIT(2) },
+ [RESET_CSI] = { CMU_DEVRST0, BIT(13) },
+ [RESET_SI] = { CMU_DEVRST0, BIT(14) },
+ [RESET_I2C0] = { CMU_DEVRST1, BIT(0) },
+ [RESET_I2C1] = { CMU_DEVRST1, BIT(1) },
+ [RESET_I2C2] = { CMU_DEVRST1, BIT(2) },
+ [RESET_I2C3] = { CMU_DEVRST1, BIT(3) },
+ [RESET_SPI0] = { CMU_DEVRST1, BIT(4) },
+ [RESET_SPI1] = { CMU_DEVRST1, BIT(5) },
+ [RESET_SPI2] = { CMU_DEVRST1, BIT(6) },
+ [RESET_SPI3] = { CMU_DEVRST1, BIT(7) },
+ [RESET_UART0] = { CMU_DEVRST1, BIT(8) },
+ [RESET_UART1] = { CMU_DEVRST1, BIT(9) },
+ [RESET_UART2] = { CMU_DEVRST1, BIT(10) },
+ [RESET_UART3] = { CMU_DEVRST1, BIT(11) },
+ [RESET_UART4] = { CMU_DEVRST1, BIT(12) },
+ [RESET_UART5] = { CMU_DEVRST1, BIT(13) },
+ [RESET_UART6] = { CMU_DEVRST1, BIT(14) },
+ [RESET_KEY] = { CMU_DEVRST1, BIT(24) },
+ [RESET_GPIO] = { CMU_DEVRST1, BIT(25) },
+ [RESET_AUDIO] = { CMU_DEVRST1, BIT(29) },
+};
+
+static struct owl_clk_desc s700_clk_desc = {
.clks = s700_clks,
.num_clks = ARRAY_SIZE(s700_clks),
.hw_clks = &s700_hw_clks,
+
+ .resets = s700_resets,
+ .num_resets = ARRAY_SIZE(s700_resets),
};
static int s700_clk_probe(struct platform_device *pdev)
{
- const struct owl_clk_desc *desc;
+ struct owl_clk_desc *desc;
+ struct owl_reset *reset;
+ int ret;
desc = &s700_clk_desc;
owl_clk_regmap_init(pdev, desc);
+ /*
+ * FIXME: Reset controller registration should be moved to
+ * common code, once all SoCs of Owl family supports it.
+ */
+ reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
+ if (!reset)
+ return -ENOMEM;
+
+ reset->rcdev.of_node = pdev->dev.of_node;
+ reset->rcdev.ops = &owl_reset_ops;
+ reset->rcdev.nr_resets = desc->num_resets;
+ reset->reset_map = desc->resets;
+ reset->regmap = desc->regmap;
+
+ ret = devm_reset_controller_register(&pdev->dev, &reset->rcdev);
+ if (ret)
+ dev_err(&pdev->dev, "Failed to register reset controller\n");
+
return owl_clk_probe(&pdev->dev, desc->hw_clks);
}