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authorClaudiu Beznea <claudiu.beznea@microchip.com>2020-11-19 17:43:14 +0200
committerStephen Boyd <sboyd@kernel.org>2020-12-19 11:50:56 -0800
commitf803858af84e1e6916edfbc5ae0fac403c02ee46 (patch)
treedd747b0edde826b9d7a33d7d983169e1ee4f7e8a /drivers/clk/at91
parent4011f03ee4756df3091ad0c2cfb0593bee8ecdf1 (diff)
clk: at91: sama7g5: decrease lower limit for MCK0 rate
On SAMA7G5 CPU clock is changed at run-time by DVFS. Since MCK0 and CPU clock shares the same parent clock (CPUPLL clock) the MCK0 is also changed by DVFS to avoid over/under clocking of MCK0 consumers. The lower limit is changed to be able to set MCK0 accordingly by DVFS. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/1605800597-16720-9-git-send-email-claudiu.beznea@microchip.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/at91')
-rw-r--r--drivers/clk/at91/sama7g5.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index 335e9c943c65..29d9781e6712 100644
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -807,7 +807,7 @@ static const struct clk_pll_characteristics pll_characteristics = {
/* MCK0 characteristics. */
static const struct clk_master_characteristics mck0_characteristics = {
- .output = { .min = 140000000, .max = 200000000 },
+ .output = { .min = 50000000, .max = 200000000 },
.divisors = { 1, 2, 4, 3, 5 },
.have_div3_pres = 1,
};