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authorMaxime Ripard <maxime@cerno.tech>2020-06-15 10:40:57 +0200
committerStephen Boyd <sboyd@kernel.org>2020-06-19 17:21:17 -0700
commit3ea59ace7c0f475bf12f13b63a47a6983959d754 (patch)
treeb581689346a192142675db0787ece52f8bdac6e9 /drivers/clk/bcm
parentc1ce3509eca684e72d0910192d5549d01558b658 (diff)
clk: bcm: rpi: Split pllb clock hooks
The driver only supports the pllb for now and all the clock framework hooks are a mix of the generic firmware interface and the specifics of the pllb. Since we will support more clocks in the future let's split the generic and specific hooks Cc: Michael Turquette <mturquette@baylibre.com> Cc: linux-clk@vger.kernel.org Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/fdc21962fdc7de5c46232f198672d5d5c868ec74.1592210452.git-series.maxime@cerno.tech Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/bcm')
-rw-r--r--drivers/clk/bcm/clk-raspberrypi.c30
1 files changed, 22 insertions, 8 deletions
diff --git a/drivers/clk/bcm/clk-raspberrypi.c b/drivers/clk/bcm/clk-raspberrypi.c
index 58ac1b104429..19571602ba64 100644
--- a/drivers/clk/bcm/clk-raspberrypi.c
+++ b/drivers/clk/bcm/clk-raspberrypi.c
@@ -102,8 +102,8 @@ static int raspberrypi_fw_is_prepared(struct clk_hw *hw)
}
-static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw,
- unsigned long parent_rate)
+static unsigned long raspberrypi_fw_get_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
{
struct raspberrypi_clk_data *data =
container_of(hw, struct raspberrypi_clk_data, hw);
@@ -116,21 +116,27 @@ static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw,
if (ret)
return ret;
- return val * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
+ return val;
}
-static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long parent_rate)
+static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ return raspberrypi_fw_get_rate(hw, parent_rate) *
+ RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
+}
+
+static int raspberrypi_fw_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
{
struct raspberrypi_clk_data *data =
container_of(hw, struct raspberrypi_clk_data, hw);
struct raspberrypi_clk *rpi = data->rpi;
- u32 new_rate = rate / RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
+ u32 _rate = rate;
int ret;
ret = raspberrypi_clock_property(rpi->firmware, data,
- RPI_FIRMWARE_SET_CLOCK_RATE,
- &new_rate);
+ RPI_FIRMWARE_SET_CLOCK_RATE, &_rate);
if (ret)
dev_err_ratelimited(rpi->dev, "Failed to change %s frequency: %d",
clk_hw_get_name(hw), ret);
@@ -138,6 +144,14 @@ static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,
return ret;
}
+static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ u32 new_rate = rate / RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
+
+ return raspberrypi_fw_set_rate(hw, new_rate, parent_rate);
+}
+
/*
* Sadly there is no firmware rate rounding interface. We borrowed it from
* clk-bcm2835.