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authorBoris Brezillon <boris.brezillon@free-electrons.com>2015-05-26 14:42:57 +0200
committerMichael Turquette <mturquette@linaro.org>2015-06-03 15:17:07 -0700
commit4d52b2acefdfceae0e47ed08324a96f511dc80b1 (patch)
tree7348889850e9f896bda2842ad0e3c15165832fad /drivers/clk/clk-cdce925.c
parent5343325ff3dd299f459fa9dacbd95dca5c9bf215 (diff)
clk: mvebu: add missing CESA gate clk
Even if not documented in the datasheet, the Armada 370 SoC can actually gate the CESA (crypto engine) clock. Add an entry in the gating_desc table to be able to reference the CESA gateclk in the crypto node. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@linaro.org>
Diffstat (limited to 'drivers/clk/clk-cdce925.c')
0 files changed, 0 insertions, 0 deletions