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authorGabriel Fernandez <gabriel.fernandez@st.com>2018-03-08 17:54:05 +0100
committerMichael Turquette <mturquette@baylibre.com>2018-03-11 15:40:34 -0700
commit3a430067838a4e47ff473999b2f6a5a7be92dba7 (patch)
tree303e72291f58449e72d526c4d82dee8626e5ae07 /drivers/clk/clk-stm32mp1.c
parent44cd455a8edb4026ae2c1c6fb6895523712c4896 (diff)
clk: stm32mp1: add Debug clocks
RCC manages clock for debug and trace. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Diffstat (limited to 'drivers/clk/clk-stm32mp1.c')
-rw-r--r--drivers/clk/clk-stm32mp1.c22
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/clk/clk-stm32mp1.c b/drivers/clk/clk-stm32mp1.c
index b3a6ec4d9e9e..f1d5967b4b39 100644
--- a/drivers/clk/clk-stm32mp1.c
+++ b/drivers/clk/clk-stm32mp1.c
@@ -260,6 +260,10 @@ static const char * const mco2_src[] = {
"ck_mpu", "ck_axi", "ck_mcu", "pll4_p", "ck_hse", "ck_hsi"
};
+static const char * const ck_trace_src[] = {
+ "ck_axi"
+};
+
static const struct clk_div_table axi_div_table[] = {
{ 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
{ 4, 4 }, { 5, 4 }, { 6, 4 }, { 7, 4 },
@@ -280,6 +284,12 @@ static const struct clk_div_table apb_div_table[] = {
{ 0 },
};
+static const struct clk_div_table ck_trace_div_table[] = {
+ { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
+ { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 },
+ { 0 },
+};
+
#define MAX_MUX_CLK 2
struct stm32_mmux {
@@ -1980,6 +1990,18 @@ static const struct clock_config stm32mp1_clock_cfg[] = {
_GATE(RCC_MCO2CFGR, 12, 0),
_MUX(RCC_MCO2CFGR, 0, 3, 0),
_DIV(RCC_MCO2CFGR, 4, 4, 0, NULL)),
+
+ /* Debug clocks */
+ FIXED_FACTOR(NO_ID, "ck_axi_div2", "ck_axi", 0, 1, 2),
+
+ GATE(DBG, "ck_apb_dbg", "ck_axi_div2", 0, RCC_DBGCFGR, 8, 0),
+
+ GATE(CK_DBG, "ck_sys_dbg", "ck_axi", 0, RCC_DBGCFGR, 8, 0),
+
+ COMPOSITE(CK_TRACE, "ck_trace", ck_trace_src, CLK_OPS_PARENT_ENABLE,
+ _GATE(RCC_DBGCFGR, 9, 0),
+ _NO_MUX,
+ _DIV(RCC_DBGCFGR, 0, 3, 0, ck_trace_div_table)),
};
struct stm32_clock_match_data {