diff options
| author | Claudiu Beznea <claudiu.beznea@microchip.com> | 2020-11-19 17:43:15 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2020-12-19 11:50:56 -0800 |
| commit | 120d5d8b4614ee26c576b29377a968093948473f (patch) | |
| tree | 16a07cc0ceafba9c7b38efc4cc60623835b90fda /drivers/clk/clk-wm831x.c | |
| parent | f803858af84e1e6916edfbc5ae0fac403c02ee46 (diff) | |
clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz
Since CPU PLL feeds both CPU clock and MCK0, MCK0 cannot go higher
than 200MHz and MCK0 maximum prescaller is 5 limit the CPU PLL at
1GHz to avoid MCK0 overclocking while CPU PLL is changed by DVFS.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-10-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/clk-wm831x.c')
0 files changed, 0 insertions, 0 deletions