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authorLoc Ho <lho@apm.com>2015-11-19 12:20:30 -0700
committerStephen Boyd <sboyd@codeaurora.org>2015-11-20 10:49:14 -0800
commit1382ea631ddddb634850a3795527db0feeff5aaf (patch)
tree72faaf0a0f6028d55cabcc7f4a4d9166c937849e /drivers/clk/clk-xgene.c
parent6dc669a22c77ad9c812bef82e186b3ab254470cb (diff)
clk: xgene: Fix divider with non-zero shift value
The X-Gene clock driver missed the divider shift operation when set the divider value. Signed-off-by: Loc Ho <lho@apm.com> Fixes: 308964caeebc ("clk: Add APM X-Gene SoC clock driver") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'drivers/clk/clk-xgene.c')
-rw-r--r--drivers/clk/clk-xgene.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/clk-xgene.c b/drivers/clk/clk-xgene.c
index 27c0da29eca3..10224b01b97c 100644
--- a/drivers/clk/clk-xgene.c
+++ b/drivers/clk/clk-xgene.c
@@ -351,7 +351,8 @@ static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate,
/* Set new divider */
data = xgene_clk_read(pclk->param.divider_reg +
pclk->param.reg_divider_offset);
- data &= ~((1 << pclk->param.reg_divider_width) - 1);
+ data &= ~((1 << pclk->param.reg_divider_width) - 1)
+ << pclk->param.reg_divider_shift;
data |= divider;
xgene_clk_write(data, pclk->param.divider_reg +
pclk->param.reg_divider_offset);