diff options
| author | Peng Fan <peng.fan@nxp.com> | 2019-10-24 01:58:42 +0000 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2019-10-25 17:07:05 +0800 |
| commit | 3f44344868cfcd76b2ca0fe334a76a17a120cdd9 (patch) | |
| tree | 7b05c5f0feaf458d0599e60a660f0e66cc9d4f04 /drivers/clk/imx/clk-divider-gate.c | |
| parent | c332481f62fa2f29af234bf85846268a5a0b173e (diff) | |
clk: imx: imx8mn: mark sys_pll1/2 as fixed clock
According Architecture definition guide, SYS_PLL1 is fixed at
800MHz, SYS_PLL2 is fixed at 1000MHz, so let's use imx_clk_fixed
to register the clocks and drop code that could change the rate.
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'drivers/clk/imx/clk-divider-gate.c')
0 files changed, 0 insertions, 0 deletions