Merge tag 'imx-clk-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next

Pull i.MX updates from Shawn Guo:

"The i.MX clock updates for 4.4:
 - A couple of fixes on i.MX31 and i.MX35 clock initialization functions
   which makes mxc_timer_init() currently be called twice for DT boot.
 - Increase i.MX6UL AXI bus clock rate to 264MHz which is the optimal
   design target.
 - Add a few missing clocks, ADC clock for i.MX7D, OCOTP clock for
   Vybrid, and SPDIF_GCLK for i.MX6.
 - A series from Lucas to fix early debug UART clock setup.  This is
   currently a one-off fix for i.MX platform, and can be extended to
   become a generic solution later."

* tag 'imx-clk-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  clk: imx6: Add SPDIF_GCLK clock in clock tree
  clk: imx7d: add ADC root clock
  clk: imx31: Do not call mxc_timer_init twice when booting with DT
  clk: imx7d: retain early UART clocks during kernel init
  clk: imx6: retain early UART clocks during kernel init
  clk: imx5: retain early UART clocks during kernel init
  clk: imx35: retain early UART clocks during kernel init
  clk: imx31: retain early UART clocks during kernel init
  clk: imx27: retain early UART clocks during kernel init
  clk: imx25: retain early UART clocks during kernel init
  clk: imx: add common logic to detect early UART usage
  clk: imx35: Do not call mxc_timer_init twice when booting with DT
  clk: clk-vf610: Add clock for Vybrid OCOTP controller
  clk: imx: increase AXI clock rate to 264MHz for i.MX6UL

1 files changed, 11 insertions, 1 deletions

diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c
index a0d4cf26cfa9..1be6230a07af 100644
--- a/drivers/clk/imx/clk-imx6sl.c
+++ b/drivers/clk/imx/clk-imx6sl.c
@@ -97,6 +97,7 @@ static struct clk_div_table video_div_table[] = {
 static unsigned int share_count_ssi1;
 static unsigned int share_count_ssi2;
 static unsigned int share_count_ssi3;
+static unsigned int share_count_spdif;
 
 static struct clk *clks[IMX6SL_CLK_END];
 static struct clk_onecell_data clk_data;
@@ -184,6 +185,12 @@ void imx6sl_set_wait_clk(bool enter)
 		imx6sl_enable_pll_arm(false);
 }
 
+static struct clk ** const uart_clks[] __initconst = {
+	&clks[IMX6SL_CLK_UART],
+	&clks[IMX6SL_CLK_UART_SERIAL],
+	NULL
+};
+
 static void __init imx6sl_clocks_init(struct device_node *ccm_node)
 {
 	struct device_node *np;
@@ -391,7 +398,8 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
 	clks[IMX6SL_CLK_PWM4]         = imx_clk_gate2("pwm4",         "perclk",            base + 0x78, 22);
 	clks[IMX6SL_CLK_SDMA]         = imx_clk_gate2("sdma",         "ipg",               base + 0x7c, 6);
 	clks[IMX6SL_CLK_SPBA]         = imx_clk_gate2("spba",         "ipg",               base + 0x7c, 12);
-	clks[IMX6SL_CLK_SPDIF]        = imx_clk_gate2("spdif",        "spdif0_podf",       base + 0x7c, 14);
+	clks[IMX6SL_CLK_SPDIF]        = imx_clk_gate2_shared("spdif",     "spdif0_podf",   base + 0x7c, 14, &share_count_spdif);
+	clks[IMX6SL_CLK_SPDIF_GCLK]   = imx_clk_gate2_shared("spdif_gclk",  "ipg",         base + 0x7c, 14, &share_count_spdif);
 	clks[IMX6SL_CLK_SSI1_IPG]     = imx_clk_gate2_shared("ssi1_ipg",     "ipg",        base + 0x7c, 18, &share_count_ssi1);
 	clks[IMX6SL_CLK_SSI2_IPG]     = imx_clk_gate2_shared("ssi2_ipg",     "ipg",        base + 0x7c, 20, &share_count_ssi2);
 	clks[IMX6SL_CLK_SSI3_IPG]     = imx_clk_gate2_shared("ssi3_ipg",     "ipg",        base + 0x7c, 22, &share_count_ssi3);
@@ -439,5 +447,7 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
 
 	clk_set_parent(clks[IMX6SL_CLK_LCDIF_AXI_SEL],
 		       clks[IMX6SL_CLK_PLL2_PFD2]);
+
+	imx_register_uart_clocks(uart_clks);
 }
 CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);