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| author | Vivek Kasireddy <vivek.kasireddy@intel.com> | 2019-07-16 19:13:16 -0700 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2019-07-18 20:26:44 +0300 |
| commit | 9a36a6517d5cc8bf7d9c1fde9058269701802e31 (patch) | |
| tree | cbcc9ec9fbc117225f1ae4d8900cd526a13a712d /drivers/clk/mediatek/clk-gate.h | |
| parent | 5270130db8c8694f7d97cc4fdc9440fb30bc2192 (diff) | |
drm/i915/ehl: Use an id of 4 while accessing DPLL4's CR0 and CR1
Although, DPLL4 enable and disable is associated with MGPLL1_ENABLE
register, we can use ICL_DPLL_CFGCR0/CR1 macros to access this dpll's
CR0 and CR1 registers by passing an id of 4 to these macros.
Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190717021316.18610-1-vivek.kasireddy@intel.com
Diffstat (limited to 'drivers/clk/mediatek/clk-gate.h')
0 files changed, 0 insertions, 0 deletions