diff options
| author | Rex-BC Chen <rex-bc.chen@mediatek.com> | 2022-05-23 17:33:34 +0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2022-06-15 17:24:12 -0700 |
| commit | 723e367114dec95abe8bba4118c4c7c3542a463f (patch) | |
| tree | c849163e4c82a05ead01bd55361052cc473c9cf5 /drivers/clk/mediatek/clk-mt7629-hif.c | |
| parent | 2d2a2900588cabe2ff3abd552d1683e5f1ce398b (diff) | |
clk: mediatek: reset: Support nonsequence base offsets of reset registers
The bank offsets are not serial for all reset registers.
For example, there are five infra reset banks for MT8192: 0x120, 0x130,
0x140, 0x150 and 0x730.
To support this,
- Change reg_ofs to rst_bank_ofs which is a pointer to base offsets of
the reset register.
- Add a new define RST_NR_PER_BANK to define reset number for each
reset bank.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220523093346.28493-8-rex-bc.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-mt7629-hif.c')
| -rw-r--r-- | drivers/clk/mediatek/clk-mt7629-hif.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/clk/mediatek/clk-mt7629-hif.c b/drivers/clk/mediatek/clk-mt7629-hif.c index 5d7ec861afab..c0583043710f 100644 --- a/drivers/clk/mediatek/clk-mt7629-hif.c +++ b/drivers/clk/mediatek/clk-mt7629-hif.c @@ -71,10 +71,12 @@ static const struct mtk_gate pcie_clks[] = { GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23), }; +static u16 rst_ofs[] = { 0x34, }; + static const struct mtk_clk_rst_desc clk_rst_desc = { .version = MTK_RST_SIMPLE, - .rst_bank_nr = 1, - .reg_ofs = 0x34, + .rst_bank_ofs = rst_ofs, + .rst_bank_nr = ARRAY_SIZE(rst_ofs), }; static int clk_mt7629_ssusbsys_init(struct platform_device *pdev) |