diff options
| author | AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2022-10-24 12:22:58 +0200 |
|---|---|---|
| committer | Chen-Yu Tsai <wenst@chromium.org> | 2022-11-29 14:42:40 +0800 |
| commit | 672c779e4cff5f4a103077e9b398f144c85db802 (patch) | |
| tree | 5bc6f8c62825b94e40de242e9524d55013551dbf /drivers/clk/mediatek/clk-mtk.c | |
| parent | 9abf2313adc1ca1b6180c508c25f22f9395cc780 (diff) | |
clk: mediatek: clk-mtk: Allow specifying flags on mtk_fixed_factor clocks
Before this change, every mtk_fixed_factor clock forced clock flags to
CLK_SET_RATE_PARENT: while this is harmless in some cases, it may not
be desired in some others, especially when performing clock muxing on
a clock having multiple parents of which one is a dedicated PLL and the
others are not.
This is especially seen on the GPU clocks on some SoCs, where we are
muxing between multiple parents: a fixed clock (crystal), a programmable
GPU PLL and one or more dividers for the MAINPLL, used for a number of
devices; it happens that when a rate change is called for the GPU, the
clock framework will try to satisfy the rate request by using one of the
MAINPLL dividers, which have CLK_SET_RATE_PARENT and will set the rate
on MAINPLL itself - overclocking or underclocking many devices in the
system - and making it to lock up.
Logically, it should be harmless (and would only reduce possible bugs)
to change all of the univpll and mainpll related fixed factor clocks
to not declare the CLK_SET_RATE_PARENT by default but, on some SoCs,
this is also used for dividers of other PLLs for which a rate change
based on the divider may be desired, hence introduce a new FACTOR_FLAGS()
macro to use custom flags (or none) on selected fixed factor clocks.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20221024102307.33722-2-angelogioacchino.delregno@collabora.com
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Diffstat (limited to 'drivers/clk/mediatek/clk-mtk.c')
| -rw-r--r-- | drivers/clk/mediatek/clk-mtk.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index d31f01d0ba1c..3c1ac8d3010f 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -149,7 +149,7 @@ int mtk_clk_register_factors(const struct mtk_fixed_factor *clks, int num, } hw = clk_hw_register_fixed_factor(NULL, ff->name, ff->parent_name, - CLK_SET_RATE_PARENT, ff->mult, ff->div); + ff->flags, ff->mult, ff->div); if (IS_ERR(hw)) { pr_err("Failed to register clk %s: %pe\n", ff->name, |