diff options
author | Chun-Jie Chen <chun-jie.chen@mediatek.com> | 2021-09-14 10:16:28 +0800 |
---|---|---|
committer | Stephen Boyd <sboyd@kernel.org> | 2021-09-14 15:05:39 -0700 |
commit | b5d728d8f1387352b354fa53b83c324618b29ba8 (patch) | |
tree | 0755897ba7e75e0b42e678f2d24693a9f2e2ff01 /drivers/clk/mediatek | |
parent | 269987505ba9c6bde73adc6cdeef22d88d5205ae (diff) |
clk: mediatek: Add MT8195 vencsys clock support
Add MT8195 vencsys clock controllers which provide clock gate
control for video encoder.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Link: https://lore.kernel.org/r/20210914021633.26377-20-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek')
-rw-r--r-- | drivers/clk/mediatek/Makefile | 3 | ||||
-rw-r--r-- | drivers/clk/mediatek/clk-mt8195-venc.c | 69 |
2 files changed, 71 insertions, 1 deletions
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 2acc12c09b06..9e330148fedf 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -84,6 +84,7 @@ obj-$(CONFIG_COMMON_CLK_MT8195) += clk-mt8195-apmixedsys.o clk-mt8195-topckgen.o clk-mt8195-peri_ao.o clk-mt8195-infra_ao.o \ clk-mt8195-cam.o clk-mt8195-ccu.o clk-mt8195-img.o \ clk-mt8195-ipe.o clk-mt8195-mfg.o clk-mt8195-scp_adsp.o \ - clk-mt8195-vdec.o clk-mt8195-vdo0.o clk-mt8195-vdo1.o + clk-mt8195-vdec.o clk-mt8195-vdo0.o clk-mt8195-vdo1.o \ + clk-mt8195-venc.o obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o diff --git a/drivers/clk/mediatek/clk-mt8195-venc.c b/drivers/clk/mediatek/clk-mt8195-venc.c new file mode 100644 index 000000000000..7339851a0856 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8195-venc.c @@ -0,0 +1,69 @@ +// SPDX-License-Identifier: GPL-2.0-only +// +// Copyright (c) 2021 MediaTek Inc. +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> + +#include "clk-gate.h" +#include "clk-mtk.h" + +#include <dt-bindings/clock/mt8195-clk.h> +#include <linux/clk-provider.h> +#include <linux/platform_device.h> + +static const struct mtk_gate_regs venc_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x8, + .sta_ofs = 0x0, +}; + +#define GATE_VENC(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &venc_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv) + +static const struct mtk_gate venc_clks[] = { + GATE_VENC(CLK_VENC_LARB, "venc_larb", "top_venc", 0), + GATE_VENC(CLK_VENC_VENC, "venc_venc", "top_venc", 4), + GATE_VENC(CLK_VENC_JPGENC, "venc_jpgenc", "top_venc", 8), + GATE_VENC(CLK_VENC_JPGDEC, "venc_jpgdec", "top_venc", 12), + GATE_VENC(CLK_VENC_JPGDEC_C1, "venc_jpgdec_c1", "top_venc", 16), + GATE_VENC(CLK_VENC_GALS, "venc_gals", "top_venc", 28), +}; + +static const struct mtk_gate venc_core1_clks[] = { + GATE_VENC(CLK_VENC_CORE1_LARB, "venc_core1_larb", "top_venc", 0), + GATE_VENC(CLK_VENC_CORE1_VENC, "venc_core1_venc", "top_venc", 4), + GATE_VENC(CLK_VENC_CORE1_JPGENC, "venc_core1_jpgenc", "top_venc", 8), + GATE_VENC(CLK_VENC_CORE1_JPGDEC, "venc_core1_jpgdec", "top_venc", 12), + GATE_VENC(CLK_VENC_CORE1_JPGDEC_C1, "venc_core1_jpgdec_c1", "top_venc", 16), + GATE_VENC(CLK_VENC_CORE1_GALS, "venc_core1_gals", "top_venc", 28), +}; + +static const struct mtk_clk_desc venc_desc = { + .clks = venc_clks, + .num_clks = ARRAY_SIZE(venc_clks), +}; + +static const struct mtk_clk_desc venc_core1_desc = { + .clks = venc_core1_clks, + .num_clks = ARRAY_SIZE(venc_core1_clks), +}; + +static const struct of_device_id of_match_clk_mt8195_venc[] = { + { + .compatible = "mediatek,mt8195-vencsys", + .data = &venc_desc, + }, { + .compatible = "mediatek,mt8195-vencsys_core1", + .data = &venc_core1_desc, + }, { + /* sentinel */ + } +}; + +static struct platform_driver clk_mt8195_venc_drv = { + .probe = mtk_clk_simple_probe, + .driver = { + .name = "clk-mt8195-venc", + .of_match_table = of_match_clk_mt8195_venc, + }, +}; +builtin_platform_driver(clk_mt8195_venc_drv); |