diff options
| author | Chun-Jie Chen <chun-jie.chen@mediatek.com> | 2021-09-14 10:16:12 +0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2021-09-14 15:05:37 -0700 |
| commit | cb95c169e95996ea9e63b9e38aa914402cfde7e3 (patch) | |
| tree | e06d42493a3999e6fef4537aa0f862789ec8824d /drivers/clk/mediatek | |
| parent | 01404648df2055ba79f85858528b723d678bd2a8 (diff) | |
clk: mediatek: Fix corner case of tuner_en_reg
On MT8195, tuner_en_reg is moved to register offest 0x0.
If we only judge by tuner_en_reg, it may lead to wrong address.
Add tuner_en_bit to the check condition. And it has been confirmed,
on all the MediaTek SoCs, bit0 of offset 0x0 is always occupied by
clock square control.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20210914021633.26377-4-chun-jie.chen@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/mediatek')
| -rw-r--r-- | drivers/clk/mediatek/clk-pll.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c index 7fb001a4e7d8..99ada6e06697 100644 --- a/drivers/clk/mediatek/clk-pll.c +++ b/drivers/clk/mediatek/clk-pll.c @@ -332,7 +332,7 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data, pll->pcw_chg_addr = pll->base_addr + REG_CON1; if (data->tuner_reg) pll->tuner_addr = base + data->tuner_reg; - if (data->tuner_en_reg) + if (data->tuner_en_reg || data->tuner_en_bit) pll->tuner_en_addr = base + data->tuner_en_reg; if (data->en_reg) pll->en_addr = base + data->en_reg; |