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authorJerome Brunet <jbrunet@baylibre.com>2019-05-13 14:31:10 +0200
committerJerome Brunet <jbrunet@baylibre.com>2019-05-20 12:18:38 +0200
commit8925dbd03bb29b1b0de30ac4e02c18faf8ddc9db (patch)
treeaf69987197af051d8fcb2d9c2210ebe54d189358 /drivers/clk/meson/gxbb.c
parentf9b3eeebef6aabaa37a351715374de53b6da860c (diff)
clk: meson: gxbb: no spread spectrum on mpll0
The documentation says there is an SSEN bit on mpll0 but, after testing it, no spread spectrum function appears to be enabled by this bit on any of the MPLLs. Let's remove it until we know more Fixes: 1f737ffa13ef ("clk: meson: mpll: fix mpll0 fractional part ignored") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/gxbb.c')
-rw-r--r--drivers/clk/meson/gxbb.c5
1 files changed, 0 insertions, 5 deletions
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 29ffb4fde714..dab16d9b1af8 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -679,11 +679,6 @@ static struct clk_regmap gxbb_mpll0_div = {
.shift = 16,
.width = 9,
},
- .ssen = {
- .reg_off = HHI_MPLL_CNTL,
- .shift = 25,
- .width = 1,
- },
.lock = &meson_clk_lock,
},
.hw.init = &(struct clk_init_data){