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authorJerome Brunet <jbrunet@baylibre.com>2018-02-19 12:21:46 +0100
committerNeil Armstrong <narmstrong@baylibre.com>2018-03-13 10:10:00 +0100
commit5b13ef64eebdc9e989fac2a3eb9aaa252a3edda6 (patch)
treea935c47e31f186223cf3ce735537d2600db3c415 /drivers/clk/meson/gxbb.c
parent05f814402d6174369b3b29832cbb5eb5ed287059 (diff)
clk: meson: clean-up clk81 clocks
clk81 is a composite clock which parents all the peripheral clocks of the platform. It is a critical clock which is used as provided by the bootloader. We don't want to change its rate or reparent it, ever. Remove the CLK_IGNORE_UNUSED on the mux and divider. These clock can't gate so the flag is useless, and the gate is already critical, so the clock won't ever be unused. Remove CLK_SET_RATE_NO_REPARENT from mux, it is useless since the mux is read-only. Remove CLK_SET_RATE_PARENT from the gate and divider and use ro_ops for the divider. A peripheral clock should not try to change the rate of clk81. Stopping the rate propagation is good way to make sure such request would be ignored. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/gxbb.c')
-rw-r--r--drivers/clk/meson/gxbb.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 70b4669cf7d6..db5e0dcbb5aa 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -775,7 +775,6 @@ static struct clk_regmap gxbb_mpeg_clk_sel = {
*/
.parent_names = clk81_parent_names,
.num_parents = ARRAY_SIZE(clk81_parent_names),
- .flags = (CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED),
},
};
@@ -787,10 +786,9 @@ static struct clk_regmap gxbb_mpeg_clk_div = {
},
.hw.init = &(struct clk_init_data){
.name = "mpeg_clk_div",
- .ops = &clk_regmap_divider_ops,
+ .ops = &clk_regmap_divider_ro_ops,
.parent_names = (const char *[]){ "mpeg_clk_sel" },
.num_parents = 1,
- .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED),
},
};
@@ -805,7 +803,7 @@ static struct clk_regmap gxbb_clk81 = {
.ops = &clk_regmap_gate_ops,
.parent_names = (const char *[]){ "mpeg_clk_div" },
.num_parents = 1,
- .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
+ .flags = CLK_IS_CRITICAL,
},
};