diff options
| author | Yixun Lan <yixun.lan@amlogic.com> | 2018-01-19 10:09:26 +0800 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2018-02-12 09:49:23 +0100 |
| commit | 2fa9b361e500a0e092a9525afbd6a3a363ffa5f0 (patch) | |
| tree | 9cd80ca23d8e175876fb35fedbba445bbb8d8368 /drivers/clk/meson | |
| parent | 6b71aceceb09918daf37a40a1221077599040be3 (diff) | |
clk: meson: axg: fix the od shift of the sys_pll
According to the datasheet, the od shift of sys_pll is actually 16.
Fixes: 78b4af312f91 ('clk: meson-axg: add clock controller drivers')
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
[fixed commit message]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk/meson')
| -rw-r--r-- | drivers/clk/meson/axg.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index a1ac0ff67e5f..455d4d8962bb 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -64,7 +64,7 @@ static struct meson_clk_pll axg_sys_pll = { }, .od = { .reg_off = HHI_SYS_PLL_CNTL, - .shift = 10, + .shift = 16, .width = 2, }, .lock = &meson_clk_lock, |