diff options
| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2018-12-02 22:42:18 +0100 |
|---|---|---|
| committer | Neil Armstrong <narmstrong@baylibre.com> | 2018-12-03 11:49:13 +0100 |
| commit | 376d8c45bd6ac79f02ecf9ca1606dc5d1b271bc0 (patch) | |
| tree | 6083166d70df9ba39746b18be764f40783b5ed48 /drivers/clk/meson | |
| parent | 21310c39ec01e82ef3ef9bf8ac385b53ccdc158c (diff) | |
clk: meson: meson8b: fix the offset of vid_pll_dco's N value
Unlike the other PLLs on Meson8b the N value "vid_pll_dco" (a better
name would be hdmi_pll_dco or - as the datasheet calls it - HPLL) is
located at HHI_VID_PLL_CNTL[14:10] instead of [13:9].
This results in an incorrect calculation of the rate of this PLL because
the value seen by the kernel is double the actual N (divider) value.
Update the offset of the N value to fix the calculation of the PLL rate.
Fixes: 28b9fcd016126e ("clk: meson8b: Add support for Meson8b clocks")
Reported-by: Jianxin Pan <jianxin.pan@amlogic.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20181202214220.7715-2-martin.blumenstingl@googlemail.com
Diffstat (limited to 'drivers/clk/meson')
| -rw-r--r-- | drivers/clk/meson/meson8b.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index f906a9f0eefd..a4ae9c957fde 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -134,7 +134,7 @@ static struct clk_regmap meson8b_vid_pll_dco = { }, .n = { .reg_off = HHI_VID_PLL_CNTL, - .shift = 9, + .shift = 10, .width = 5, }, .l = { |