diff options
| author | Michael Turquette <mturquette@baylibre.com> | 2016-04-28 17:18:52 -0700 |
|---|---|---|
| committer | Michael Turquette <mturquette@baylibre.com> | 2016-06-22 18:01:56 -0700 |
| commit | 89ef4b6217566f3429a577b84fc67b3a6463e26c (patch) | |
| tree | 68df57afee068a38440b951da5108163b937edeb /drivers/clk/meson | |
| parent | 1a695a905c18548062509178b98bc91e67510864 (diff) | |
clk: meson8b: rectify reg offsets with datasheet
The register offsets in the data sheet are confusing. Document them more
thoroughly.
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Diffstat (limited to 'drivers/clk/meson')
| -rw-r--r-- | drivers/clk/meson/meson8b-clkc.c | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/drivers/clk/meson/meson8b-clkc.c b/drivers/clk/meson/meson8b-clkc.c index 4d057b3e21b2..444ef9414797 100644 --- a/drivers/clk/meson/meson8b-clkc.c +++ b/drivers/clk/meson/meson8b-clkc.c @@ -24,10 +24,19 @@ #include "clkc.h" +/* + * Clock controller register offsets + * + * Register offsets from the HardKernel[0] data sheet are listed in comment + * blocks below. Those offsets must be multiplied by 4 before adding them to + * the base address to get the right value + * + * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf + */ #define MESON8B_REG_CTL0_ADDR 0x0000 -#define MESON8B_REG_SYS_CPU_CNTL1 0x015c -#define MESON8B_REG_HHI_MPEG 0x0174 -#define MESON8B_REG_MALI 0x01b0 +#define MESON8B_REG_SYS_CPU_CNTL1 0x015c /* 0x57 offset in data sheet */ +#define MESON8B_REG_HHI_MPEG 0x0174 /* 0x5d offset in data sheet */ +#define MESON8B_REG_MALI 0x01b0 /* 0x6c offset in data sheet */ #define MESON8B_REG_PLL_FIXED 0x0280 #define MESON8B_REG_PLL_SYS 0x0300 #define MESON8B_REG_PLL_VID 0x0320 |