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authorJerome Brunet <jbrunet@baylibre.com>2021-04-29 11:03:25 +0200
committerJerome Brunet <jbrunet@baylibre.com>2021-05-20 18:01:56 +0200
commitbc794f8c56abddf709f1f84fcb2a3c9e7d9cc9b4 (patch)
treed154ded97d6dd8b3931b8615e77f6fd3d594a146 /drivers/clk/meson
parent4cbf0cd6bf4c704746b6a6c6d42a8ee327070005 (diff)
clk: meson: g12a: fix gp0 and hifi ranges
While some SoC samples are able to lock with a PLL factor of 55, others samples can't. ATM, a minimum of 60 appears to work on all the samples I have tried. Even with 60, it sometimes takes a long time for the PLL to eventually lock. The documentation says that the minimum rate of these PLLs DCO should be 3GHz, a factor of 125. Let's use that to be on the safe side. With factor range changed, the PLL seems to lock quickly (enough) so far. It is still unclear if the range was the only reason for the delay. Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lore.kernel.org/r/20210429090325.60970-1-jbrunet@baylibre.com
Diffstat (limited to 'drivers/clk/meson')
-rw-r--r--drivers/clk/meson/g12a.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index b080359b4645..a805bac93c11 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -1603,7 +1603,7 @@ static struct clk_regmap g12b_cpub_clk_trace = {
};
static const struct pll_mult_range g12a_gp0_pll_mult_range = {
- .min = 55,
+ .min = 125,
.max = 255,
};